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enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 revision: v1.90 date: ? e ??? a?? 18? ?01? ? e??? a?? 18 ? ?01?
rev. 1.90 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom table of contents eates cpu ? eat ?? es ........................................................................................................................ 8 pe ? iphe ? al ? eat ?? es ................................................................................................................ 9 gene?al desc?iption ....................................................................................... 10 selection ta?le ................................................................................................ 11 block diag?am ................................................................................................ 1? pin assignment .............................................................................................. 1? pin desc?iption .............................................................................................. 17 a?sol?te maxim?m ratings .......................................................................... ?? d.c. cha?acte?istics ....................................................................................... ?4 a.c. cha?acte?istics ....................................................................................... ?5 a/d conve?te? cha?acte?istics ...................................................................... ?6 compa?ato? elect?ical cha?acte?istics ........................................................ ?7 powe?-on reset cha?acte?istics ................................................................... ?7 s?stem a?chitect??e ...................................................................................... ?8 clocking and pipelining ......................................................................................................... ? 8 p ? og ? am co ? nte ? ................................................................................................................... ? 9 stack ..................................................................................................................................... ? 0 a ? ithmetic and logic unit C alu ........................................................................................... ? 0 ?lash p?og?am memo?? ................................................................................. ?1 st ?? ct ?? e ................................................................................................................................ ? 1 special vecto ? s ..................................................................................................................... ?? look- ? p ta ? le ........................................................................................................................ ?? ta ? le p ? og ? am example ........................................................................................................ ?? in ci ? c ? it p ? og ? amming C icp ............................................................................................... ? 4 data memo?? .................................................................................................. ?5 st ?? ct ?? e ................................................................................................................................ ? 5 special ??nction registe? desc?iption ........................................................ ?9 indi ? ect add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 9 memo ?? pointe ? s C mp0 ? mp1 .............................................................................................. ? 9 bank pointe ? C bp ................................................................................................................. 40 acc ? m ? lato ? C acc ............................................................................................................... 4 ? p ? og ? am co ? nte ? low registe ? C pcl .................................................................................. 4 ? look- ? p ta ? le registe ? s C tblp ? tbhp ? tblh ..................................................................... 4 ? stat ? s registe ? C status .................................................................................................... 4 ?
rev. 1.90 ? ?e???a?? 18? ?01? rev. 1.90 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom eeprom data memory .................................................................................. 45 eeprom data memo ?? st ?? ct ?? e ........................................................................................ 45 eeprom registe ? s .............................................................................................................. 45 reading data f ? om the eeprom ......................................................................................... 49 w ? iting data to the eeprom ................................................................................................ 49 w ? ite p ? otection ..................................................................................................................... 49 eeprom inte ??? pt ................................................................................................................ 49 p ? og ? amming conside ? ations ................................................................................................ 50 p ? og ? amming examples ........................................................................................................ 50 oscillator ........................................................................................................ 51 oscillato ? ove ? view ............................................................................................................... 51 system clock confgurations ................................................................................................ 51 exte ? nal c ?? stal/ce ? amic oscillato ? C hxt ........................................................................... 5 ? exte ? nal rc oscillato ? C erc ............................................................................................... 54 inte ? nal high speed rc oscillato ? C hirc ........................................................................... 54 exte ? nal ?? .768khz c ?? stal oscillato ? C lxt ........................................................................ 55 inte ? nal low speed oscillato ? C lirc ................................................................................... 56 s ? pplementa ?? oscillato ? s .................................................................................................... 56 operating modes and system clocks ......................................................... 57 s ? stem clock ........................................................................................................................ 57 s ? stem ope ? ation modes ...................................................................................................... 59 cont ? ol registe ? .................................................................................................................... 60 ? ast wake- ? p ........................................................................................................................ 6 ? ope ? ating mode switching .................................................................................................... 6 ? normal mode to slow mode switching ........................................................................... 64 slow mode to normal mode switching ........................................................................... 65 ente ? ing the sleep0 mode .................................................................................................. 66 ente ? ing the sleep1 mode .................................................................................................. 66 ente ? ing the idle0 mode ...................................................................................................... 66 ente ? ing the idle1 mode ...................................................................................................... 67 stand ?? c ??? ent conside ? ations ........................................................................................... 67 wake- ? p ................................................................................................................................ 68 p ? og ? amming conside ? ations ................................................................................................ 68 watchdog timer ............................................................................................. 69 watchdog time ? clock so ?? ce .............................................................................................. 69 watchdog time ? cont ? ol registe ? ......................................................................................... 69 watchdog time ? ope ? ation ................................................................................................... 70 reset and initialisation .................................................................................. 71 reset ?? nctions .................................................................................................................... 71 reset initial conditions ......................................................................................................... 74
rev. 1.90 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom input/output ports ......................................................................................... 84 p ? ll-high resisto ? s ................................................................................................................ 87 po ? t a wake- ? p ..................................................................................................................... 89 i/o po ? t cont ? ol registe ? s ..................................................................................................... 89 pin- ? emapping ?? nctions ...................................................................................................... 9 ? pin- ? emapping registe ? s ....................................................................................................... 9 ? i/o pin st ?? ct ?? es .................................................................................................................. 99 p ? og ? amming conside ? ations .............................................................................................. 100 timer modules C tm .................................................................................... 100 int ? od ? ction ......................................................................................................................... 100 tm ope ? ation ...................................................................................................................... 101 tm clock so ?? ce ................................................................................................................. 101 tm inte ??? pts ....................................................................................................................... 101 tm exte ? nal pins ................................................................................................................. 10 ? tm inp ? t/o ? tp ? t pin cont ? ol registe ? s ............................................................................... 10 ? p ? og ? amming conside ? ations ............................................................................................... 11 ? compact type tm C ctm ............................................................................. 113 compact tm ope ? ation ........................................................................................................ 11 ? compact t ? pe tm registe ? desc ? iption ............................................................................... 114 compact t ? pe tm ope ? ating modes ................................................................................... 118 compa ? e match o ? tp ? t mode .............................................................................................. 118 time ? /co ? nte ? mode ............................................................................................................ 118 pwm o ? tp ? t mode .............................................................................................................. 1 ? 1 standard type tm C stm ............................................................................ 124 standa ? d tm ope ? ation ....................................................................................................... 1 ? 4 standa ? d t ? pe tm registe ? desc ? iption ............................................................................. 1 ? 5 standa ? d t ? pe tm ope ? ating modes .................................................................................. 1 ? 4 compa ? e match o ? tp ? t mode ............................................................................................. 1 ? 4 time ? /co ? nte ? mode ........................................................................................................... 1 ? 7 pwm o ? tp ? t mode .............................................................................................................. 1 ? 7 single p ? lse mode .............................................................................................................. 141 capt ?? e inp ? t mode ............................................................................................................ 14 ? enhanced type tm C etm ........................................................................... 145 enhanced tm ope ? ation ..................................................................................................... 146 enhanced t ? pe tm registe ? desc ? iption ............................................................................ 146 enhanced t ? pe tm ope ? ating modes ................................................................................. 15 ? compa ? e o ? tp ? t mode ........................................................................................................ 154 time ? /co ? nte ? mode ........................................................................................................... 159 pwm o ? tp ? t mode .............................................................................................................. 159 single p ? lse mode .............................................................................................................. 165 capt ?? e inp ? t mode ............................................................................................................ 167
rev. 1.90 4 ?e???a?? 18? ?01? rev. 1.90 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom aanlog to digital converter ........................................................................ 170 a/d ove ? view ...................................................................................................................... 170 a/d conve ? te ? registe ? desc ? iption .................................................................................... 170 a/d ope ? ation ..................................................................................................................... 176 a/d inp ? t pins ..................................................................................................................... 177 s ? mma ?? of a/d conve ? sion steps ..................................................................................... 177 p ? og ? amming conside ? ations .............................................................................................. 179 a/d t ? ansfe ? ?? nction ......................................................................................................... 179 a/d p ? og ? amming example ................................................................................................. 180 comparators ................................................................................................ 182 compa ? ato ? ope ? ation ........................................................................................................ 18 ? compa ? ato ? registe ? s ......................................................................................................... 18 ? compa ? ato ? inte ??? pt ........................................................................................................... 185 p ? og ? amming conside ? ations .............................................................................................. 185 serial interface module C sim ..................................................................... 186 spi inte ? face ....................................................................................................................... 186 spi registe ? s ...................................................................................................................... 188 spi comm ? nication ............................................................................................................ 191 i ? c inte ? face ........................................................................................................................ 19 ? i ? c inte ? face ope ? ation ........................................................................................................ 19 ? i ? c registe ? s ....................................................................................................................... 194 i ? c b ? s comm ? nication ...................................................................................................... 198 i ? c b ? s sta ? t signal ............................................................................................................. 199 slave add ? ess ..................................................................................................................... 199 i ? c b ? s read/w ? ite signal .................................................................................................. ? 00 i ? c b ? s slave add ? ess acknowledge signal ....................................................................... ? 00 i ? c b ? s data and acknowledge signal ............................................................................... ? 00 peripheral clock output .............................................................................. 202 pe ? iphe ? al clock ope ? ation ................................................................................................. ? 0 ? interrupts ...................................................................................................... 203 inte ??? pt registe ? s ............................................................................................................... ? 0 ? inte ??? pt ope ? ation .............................................................................................................. ? 17 exte ? nal inte ??? pt ................................................................................................................. ?? 1 compa ? ato ? inte ??? pt ........................................................................................................... ?? 1 m ? lti-f ? nction inte ??? pt ........................................................................................................ ?? 1 a/d conve ? te ? inte ??? pt ....................................................................................................... ??? time base inte ??? pt ............................................................................................................. ??? se ? ial inte ? face mod ? le inte ??? pt ......................................................................................... ?? 4 exte ? nal pe ? iphe ? al inte ??? pt ............................................................................................... ?? 4 eeprom inte ??? pt .............................................................................................................. ?? 4 lvd inte ??? pt ....................................................................................................................... ?? 5 tm inte ??? pts ....................................................................................................................... ?? 5 inte ??? pt wake- ? p ?? nction ................................................................................................. ?? 6 p ? og ? amming conside ? ations .............................................................................................. ?? 6
rev. 1.90 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom power down mode and wake-up ................................................................ 227 ente ? ing the idle o ? sleep mode ..................................................................................... ?? 7 stand ?? c ??? ent conside ? ations ......................................................................................... ?? 7 wake- ? p .............................................................................................................................. ?? 8 low voltage detector C lvd ....................................................................... 229 lvd registe ? ....................................................................................................................... ?? 9 lvd ope ? ation ..................................................................................................................... ?? 0 scom function for lcd .............................................................................. 231 lcd ope ? ation .................................................................................................................... ?? 1 lcd bias cont ? ol ................................................................................................................ ??? confguration options ................................................................................. 234 application circuits ..................................................................................... 235 uart module serial interface .................................................................... 236 uart mod ? le ? eat ?? es ....................................................................................................... ?? 6 uart mod ? le ove ? view ...................................................................................................... ?? 6 uart mod ? le block diag ? am ............................................................................................. ?? 6 pin assignment ................................................................................................................... ?? 7 uart mod ? le pin desc ? iption ............................................................................................. ?? 9 uart mod ? le d.c. cha ? acte ? istics ..................................................................................... ? 40 uart mod ? le a.c. cha ? acte ? istics ..................................................................................... ? 41 uart mod ? le ?? nctional desc ? iption ................................................................................. ? 41 uart mod ? le inte ? nal signal .............................................................................................. ? 41 uart mod ? le spi inte ? face ................................................................................................ ? 4 ? uart mod ? le exte ? nal pin inte ? facing ................................................................................ ? 4 ? uart data t ? ansfe ? scheme .............................................................................................. ? 4 ? uart commands ............................................................................................................... ? 44 uart stat ? s and cont ? ol registe ? s .................................................................................... ? 44 ba ? d rate gene ? ato ? .......................................................................................................... ? 50 uart mod ? le set ? p and cont ? ol ........................................................................................ ? 5 ? managing receive ? e ?? o ? s .................................................................................................. ? 57 uart mod ? le inte ??? pt st ?? ct ?? e ........................................................................................ ? 58 uart mod ? le powe ? -down and wake- ? p .......................................................................... ? 59 using the uart ?? nction .................................................................................................... ? 60 application ci ? c ? it with uart mod ? le ................................................................................. ? 61 instruction set .............................................................................................. 262 int ? od ? ction ......................................................................................................................... ? 6 ? inst ?? ction timing ................................................................................................................ ? 6 ? moving and t ? ansfe ?? ing data ............................................................................................. ? 6 ? a ? ithmetic ope ? ations .......................................................................................................... ? 6 ? logical and rotate ope ? ation ............................................................................................. ? 6 ? b ? anches and cont ? ol t ? ansfe ? ........................................................................................... ? 6 ? bit ope ? ations ..................................................................................................................... ? 6 ? ta ? le read ope ? ations ....................................................................................................... ? 6 ? othe ? ope ? ations ................................................................................................................. ? 6 ?
rev. 1.90 6 ?e???a?? 18? ?01? rev. 1.90 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom instruction set summary ............................................................................ 264 ta ? le conventions ............................................................................................................... ? 64 instruction defnition ................................................................................... 266 package information ................................................................................... 275 16-pin dip ( ? 00mil) o ? tline dimensions ............................................................................. ? 75 16-pin nsop (150mil) o ? tline dimensions ......................................................................... ? 78 16-pin ssop (150mil) o ? tline dimensions ......................................................................... ? 79 ? 0-pin dip ( ? 00mil) o ? tline dimensions ............................................................................. ? 80 ? 0-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... ? 8 ? ? 0-pin ssop (150mil) o ? tline dimensions ......................................................................... ? 8 ? ? 4-pin skdip ( ? 00mil) o ? tline dimensions ........................................................................ ? 84 ? 4-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... ? 87 ? 4-pin ssop (150mil) o ? tline dimensions ......................................................................... ? 88 ? 8-pin skdip ( ? 00mil) o ? tline dimensions ........................................................................ ? 89 ? 8-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... ? 90 ? 8-pin ssop (150mil) o ? tline dimensions ......................................................................... ? 91 saw t ? pe ?? -pin (5mm5mm) q ? n o ? tline dimensions .................................................. ? 9 ? saw t ? pe 40-pin (6mm6mm) q ? n o ? tline dimensions .................................................. ? 9 ? 44-pin lq ? p (10mm10mm) ( ? p ? .0mm) o ? tline dimensions .......................................... ? 94 48-pin ssop ( ? 00mil) o ? tline dimensions ......................................................................... ? 95 saw t ? pe 48-pin (7mm7mm) q ? n o ? tline dimensions .................................................. ? 96 48-pin lq ? p (7mm7mm) o ? tline dimensions .................................................................. ? 97 5 ? -pin q ? p (14mm14mm) o ? tline dimensions ................................................................ ? 98 reel dimensions ................................................................................................................. ? 99 ca ?? ie ? tape dimensions ..................................................................................................... ? 01 ca ?? ie ? tape dimensions ..................................................................................................... ? 06
rev. 1.90 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom features cpu features ? operating voltage: f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? five oscillators: external crystal -- hxt external 32.768khz crystal -- lxt external rc -- erc internal rc -- hirc internal 32khz rc -- lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 12-level subroutine nesting ? bit manipulation instruction
rev. 1.90 8 ?e???a?? 18? ?01? rev. 1.90 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom peripheral features ? flash program memory: 1k14~12k16 ? ram data memory: 648~5768 ? eeprom memory: 328~2568 ? watchdog timer function ? up to 50 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias ? multiple pin-shared external interrupts ? multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output function ? serial interfaces module -- sim for spi or i 2 c ? dual comparator functions ? dual time-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? optional peripheral -- uart module for fully duplex asynchronous communication ? wide range of available package types ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? eeprom data memory can be re-programmed up to 1,000,000 times ? eeprom data memory data retention > 10 years
rev. 1.90 10 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 11 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom general description the ht66fxx series of devices are flash memory a/d type 8-bit high performance risc architecture microcontrollers. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation fun ctions. com munication wit h th e out side worl d is ca tered for by in cluding ful ly integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy co mmunication wit h ex ternal pe ripheral ha rdware. pro tective fe atures suc h as an internalwatchdog timer , low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the uart module is contained in the ht66fux0 series of devices. it can support the applications such as data communication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and battery operated device communication, etc. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure tha t the devi ces wil l fnd exc ellent use in appl ications such as el ectronic me tering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others.
rev. 1.90 10 ?e???a?? 18? ?01? rev. 1.90 11 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom selection table most feat ures are c ommon t o a ll devic es, t he ma in feat ure dist inguishing them are me mory capac ity, i/o count, tm features, stack capacity and package types. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. int. a/d timer module interface (spi/i 2 c) uart stacks package ht66 ?? 0 ? . ? v~5.5v 1k14 648 ?? 8 18 ? 1 ? - ? it8 10- ? it ctm1 ? 10- ? it stm1 4 16dip/nsop/ssop ? 0dip/sop/ssop ht66 ?? 0 ? . ? v~5.5v ? k14 968 648 ?? ? 1 ? - ? it8 10- ? it ctm1 ? 10- ? it etm1 4 16dip/nsop/ssop ? 0dip/sop/ssop ? 4skdip/sop/ssop ht66 ? u ? 0 14 ? 4skdip/sop ht66 ? 40 ? . ? v~5.5v 4k15 19 ? 8 1 ? 88 4 ? ? 1 ? - ? it8 10- ? it ctm1 ? 10- ? it etm1 ? 16- ? it stm1 8 ? 4/ ? 8skdip/sop/ssop 44lq ? p ?? /40q ? n ? 48ssop/q ? n ht66 ? u40 ? 4 40q ? n ? 44lq ? p ? 48ssop/q ? n ht66 ? 50 ? . ? v~5.5v 8k16 ? 848 ? 568 4 ? ? 1 ? - ? it8 10- ? it ctm ?? 10- ? it etm1 ? 16- ? it stm1 8 ? 8skdip/sop/ssop 44lq ? p ? 40q ? n 48ssop/q ? n ht66 ? u50 ? 4 44lq ? p ? 48q ? n ht66 ? 60 ? . ? v~5.5v 1 ? k16 5768 ? 568 50 4 1 ? - ? it1 ? 10- ? it ctm ?? 10- ? it etm1 ? 16- ? it stm1 1 ? 5 ? q ? p ? 40q ? n ? 44lq ? p 48ssop/lq ? p/q ? n ht66 ? u60 4 ? 5 ? q ? p ? 40q ? n ? 44lq ? p 48lq ? p/q ? n note: as devices exist in more than one package format, the table refects the situation for the package with the most pins. there is an additional peripheral known as the uart module in ht66fu30, ht66fu40, ht66fu50 and HT66FU60 devices. all information related to the uart module will be described in the following uart module section.
rev. 1.90 1 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom block diagram
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rev. 1.90 1? ?e???a?? 18? ?01? rev. 1.90 1 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin assignment

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rev. 1.90 14 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 15 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.90 14 ?e???a?? 18? ?01? rev. 1.90 15 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.90 16 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 17 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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? ? ? ? ? note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority. 3. vdd&avdd means the vdd and avdd are the double bonding.
rev. 1.90 16 ?e???a?? 18? ?01? rev. 1.90 17 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin description with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. the following ta bles onl y inc lude the pin s whic h are di rectly rel ated to the mcu. the pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description. ht66f20 pin name function op i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb5 po ? t b pbpu st cmos pc0~pc ? po ? t c pcpu st cmos an0~an7 adc inp ? t acerl an pa0~pa7 vre ? adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cmos pa0 ? pa5 tck0 ? tck1 tm0 ? tm1 inp ? t st pa ?? pa4 tp0_0 tm0 i/o tmpc0 st cmos pa0 tp1_0 ? tp1_1 tm1 i/o tmpc0 st cmos pa1 ? pc0 int0 ? int1 ext. inte ??? pt 0 ? 1 st pa ?? pa4 pint pe ? iphe ? al inte ??? pt st pc ? pck pe ? iphe ? al clock o ? tp ? t cmos pc ? sdi spi data inp ? t st pa6 sdo spi data o ? tp ? t cmos pa5 scs spi slave select st cmos pb5 sck spi se ? ial clock st cmos pa7 scl i ? c clock st nmos pa7 sda i ? c data st nmos pa6 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc ?? pc ? osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd** pwr avss adc g ? o ? nd** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin
rev. 1.90 18 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 19 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is th e de vice powe r suppl y whil e avdd is th e adc powe r suppl y. th e avdd pi n is bon ded together internally with vdd. **: vss is th e de vice gr ound pi n whi le avss is th e adc gr ound pi n. th e avss pi n is bo nded to gether internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht66f30 pin name function op i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb5 po ? t b pbpu st cmos pc0~pc7 po ? t c pcpu st cmos an0~an7 adc inp ? t acerl an pa0~pa7 vre ? adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cmos pa0 ? pa5 tck0 ? tck1 tm0 ? tm1 inp ? t st pa ?? pa4 tp0_0 ? tp0_1 tm0 i/o tmpc0 st cmos pa0 ? pc5 tp1a tm1 i/o tmpc0 st cmos pa1 tp1b_0 ? tp1b_1 tm1 i/o tmpc0 st cmos pc0 ? pc1 int0 ? int1 ext. inte ??? pt 0 ? 1 st pa ?? pa4 pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pc0 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pc1 scs spi slave select prm0 st cmos pb5 o ? pc6 sck spi se ? ial clock prm0 st cmos pa7 o ? pc7 scl i ? c clock prm0 st nmos pa7 o ? pc7 sda i ? c data prm0 st nmos pa6 o ? pc0 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc7 osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd** pwr avss adc g ? o ? nd** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin
rev. 1.90 18 ?e???a?? 18? ?01? rev. 1.90 19 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is th e de vice powe r suppl y whil e avdd is th e adc powe r suppl y. th e avdd pi n is bon ded together internally with vdd. **: vss is th e de vice gr ound pi n whi le avss is th e adc gr ound pi n. th e avss pi n is bo nded to gether internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht66f40 pin name function op i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb7 po ? t b pbpu st cmos pc0~pc7 po ? t c pcpu st cmos pd0~pd7 po ? t d pdpu st cmos pe0~pe7 po ? t e pepu st cmos p ? 0~p ? 1 po ? t ? p ? pu st cmos an0~an7 adc inp ? t acerl an pa0~pa7 vre ? adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cp0c cp1c prm0 cmos pa0 ? pa5 o ? p ? 0 ? p ? 1 tck0~tck ? tm0~tm ? inp ? t prm1 st pa ?? pa4 ? pc ? o ? pd ?? pd ?? pd0 tp0_0 ? tp0_1 tm0 i/o tmpc0 prm ? st cmos pa0 ? pc5 o ? pc6 ? pd5 tp1a tm1 i/o tmpc0 prm ? st cmos pa1 o ? pc7 tp1b_0~tp1b_ ? tm1 i/o tmpc0 prm ? st cmos pc0 ? pc1 ? pc5 ? o ? - ? - ? pe4 tp ? _0 ? tp ? _1 tm ? i/o tmpc1 prm ? st cmos pc ?? pc4 o ? pd1 ? pd4 int0 ? int1 ext. inte ??? pt 0 ? 1 prm1 st pa ?? pa4 o ? pc4 ? pc5 o ? pe6 ? pe7 pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pd ? o ? pb7 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pd ? o ? pb6 scs spi slave select prm0 st cmos pb5 o ? pd0 o ? pd7 sck spi se ? ial clock prm0 st cmos pa7 o ? pd1 o ? pd6 scl i ? c clock prm0 st nmos pa7 o ? pd1 o ? pd6 sda i ? c data prm0 st nmos pa6 o ? pd ? o ? pb7 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc7 osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4
rev. 1.90 ? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin name function op i/t o/t pin-shared mapping res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd** pwr avss adc g ? o ? nd** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is th e de vice powe r suppl y whil e avdd is th e adc powe r suppl y. th e avdd pi n is bon ded together internally with vdd. **: vss is th e de vice gr ound pi n whi le avss is th e adc gr ound pi n. th e avss pi n is bo nded to gether internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht66f50 pin name function op i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb7 po ? t b pbpu st cmos pc0~pc7 po ? t c pcpu st cmos pd0~pd7 po ? t d pdpu st cmos pe0~pe7 po ? t e pepu st cmos p ? 0~p ? 1 po ? t ? p ? pu st cmos an0~an7 adc inp ? t acerl an pa0~pa7 vre ? adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cp0c cp1c prm0 cmos pa0 ? pa5 o ? p ? 0 ? p ? 1 tck0~tck ? tm0~tm ? inp ? t prm1 st pa ?? pa4 ? pc ?? pc4 o ? pd ?? pd ?? pd0 ? C tp0_0 ? tp0_1 tm0 i/o tmpc0 prm ? st cmos pa0 ? pc5 o ? pc6 ? pd5 tp1a tm1 i/o tmpc0 prm ? st cmos pa1 o ? pc7 tp1b_0~tp1b_ ? tm1 i/o tmpc0 prm ? st cmos pc0 ? pc1 ? pc5 o ? C ? C pe4 tp ? _0 ? tp ? _1 tm ? i/o tmpc1 prm ? st cmos pc ?? pc4 o ? pd1 ? pd4 tp ? _0 ? tp ? _1 tm ? i/o tmpc1 prm ? st cmos pd ?? pd0 o ? pe5 ? pe ?
rev. 1.90 ?0 ?e???a?? 18? ?01? rev. 1.90 ? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin name function op i/t o/t pin-shared mapping int0 ? int1 ext. inte ??? pt 0 ? 1 prm1 st pa ?? pa4 o ? pc4 ? pc5 o ? pe6 ? pe7 pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pd ? o ? pb7 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pd ? o ? pb6 scs spi slave select prm0 st cmos pb5 o ? pd0 o ? pd7 sck spi se ? ial clock prm0 st cmos pa7 o ? pd1 o ? pd6 scl i ? c clock prm0 st nmos pa7 o ? pd1 o ? pd6 sda i ? c data prm0 st nmos pa6 o ? pd ? o ? pb7 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc7 osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd** pwr avss adc g ? o ? nd** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is th e de vice powe r suppl y whil e avdd is th e adc powe r suppl y. th e avdd pi n is bon ded together internally with vdd. **: vss is th e de vice gr ound pi n whi le avss is th e adc gr ound pi n. th e avss pi n is bo nded to gether internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins.
rev. 1.90 ?? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f60 pin name function op i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb7 po ? t b pbpu st cmos pc0~pc7 po ? t c pcpu st cmos pd0~pd7 po ? t d pdpu st cmos pe0~pe7 po ? t e pepu st cmos p ? 0~p ? 7 po ? t ? p ? pu st cmos pg0~pg1 po ? t g pgpu st cmos an0~an11 adc inp ? t acerl acerh an pa0~pa7 ? pe6 ? pe7 ? p ? 0 ? p ? 1 vre ? adc ? efe ? ence inp ? t adcr1 an pb5 c0- ? c1- compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0+ ? c1+ compa ? ato ? 0 ? 1 inp ? t cp0c cp1c an pa ?? pc ? c0x ? c1x compa ? ato ? 0 ? 1 o ? tp ? t cp0c cp1c prm0 cmos pa0 ? pa5 o ? p ? 0 ? p ? 1 o ? pg0 ? pg1 tck0~tck ? tm0~tm ? inp ? t prm1 st pa ?? pa4 ? pc ?? pc4 o ? pd ?? pd ?? pd0 ? C tp0_0 ? tp0_1 tm0 i/o tmpc0 prm ? st cmos pa0 ? pc5 o ? pc6 ? pd5 tp1a tm1 i/o tmpc0 prm ? st cmos pa1 o ? pc7 tp1b_0~tp1b_ ? tm1 i/o tmpc0 prm ? st cmos pc0 ? pc1 ? pc5 o ? C ? C ? pe4 tp ? _0 ? tp ? _1 tm ? i/o tmpc1 prm ? st cmos pc ?? pc4 o ? pd1 ? pd4 tp ? _0 ? tp ? _1 tm ? i/o tmpc1 prm ? st cmos pd ?? pd0 o ? pe5 ? pe ? int0~int ? ext. inte ??? pt 0~ ? prm1 st pa ?? pa4 ? pc4 ? pc5 o ? pc4 ? pc5 ? pe ?? C ? o ? pe0 ? pe1 ? C ? C o ? pe6 ? pe7 ? C ? C pint pe ? iphe ? al inte ??? pt prm0 st pc ? o ? pc4 pck pe ? iphe ? al clock o ? tp ? t prm0 cmos pc ? o ? pc5 sdi spi data inp ? t prm0 st pa6 o ? pd ? o ? pb7 sdo spi data o ? tp ? t prm0 cmos pa5 o ? pd ? o ? pb6 o ? pd1 scs spi slave select prm0 st cmos pb5 o ? pd0 o ? pd7 sck spi se ? ial clock prm0 st cmos pa7 o ? pd1 o ? pd6 o ? pd ? scl i ? c clock prm0 st nmos pa7 o ? pd1 o ? pd6 o ? pd ? sda i ? c data prm0 st nmos pa6 o ? pd ? o ? pb7 scom0~scom ? scom0~scom ? scomc scom pc0 ? pc1 ? pc6 ? pc7 osc1 hxt/erc pin co hxt pb1 osc ? hxt pin co hxt pb ? xt1 lxt pin co lxt pb ? xt ? lxt pin co lxt pb4 res reset inp ? t co st pb0 vdd powe ? s ? ppl ? * pwr
rev. 1.90 ?? ?e???a?? 18? ?01? rev. 1.90 ?? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin name function op i/t o/t pin-shared mapping avdd adc powe ? s ? ppl ? * pwr vss g ? o ? nd** pwr avss adc g ? o ? nd** pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is th e de vice powe r suppl y whil e avdd is th e adc powe r suppl y. th e avdd pi n is bon ded together internally with vdd. **: vss is th e de vice gr ound pi n whi le avss is th e adc gr ound pi n. th e avss pi n is bo nded to gether internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature .................................................................................................... -50? c to 125?c operating temperature .................................................................................................. -40? c to 85 ?c i oh total .................................................................................................................................... -80ma i ol total ..................................................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw note: these are str ess rat ings only . stre sses exc eeding the range spec ified unde r "absolu te max imum ratings" may ca use sub stantial da mage to th ese de vices. fun ctional op eration of th ese de vices at other conditions bey ond th ose li sted in th e spec ifcation is not im plied and prol onged exp osure to extreme conditions may affect devices reliability.
rev. 1.90 ? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage ( hxt ? erc ? hirc ) f sys =8mhz ? . ? 5.5 v f sys = 1 ? mhz ? .7 5.5 v f sys = ? 0 mhz 4.5 5.5 v i dd1 ope ? ating c ??? ent ? no ? mal mode ? f sys =f h ( hxt ? erc ? hirc) ? v no load ? f sys =f h =4mhz ? adc off ? wdt ena ? le 0.7 1.1 ma 5v 1.8 ? .7 ma ? v no load ? f sys =f h =8mhz ? adc off ? wdt ena ? le 1.6 ? .4 ma 5v ? . ? 5.0 ma ? v no load ? f sys =f h =1 ? mhz ? adc off ? wdt ena ? le ? . ? ? . ? ma 5v 5.0 7.5 ma i dd ? ope ? ating c ??? ent ? no ? mal mode ? f sys =f h (hxt) 5v no load ? f sys =f h = ? 0 mhz ? adc off ? wdt ena ? le 6.0 9.0 ma i dd ? ope ? ating c ??? ent ? slow mode ? f sys =f l (l xt ? lirc) ? v no load ? f sys =f l ? adc off ? wdt ena ? le 10 ? 0 a 5v ? 0 50 a i idle0 idle0 mode stand ?? c ??? ent (lxt o ? lirc on) ? v no load ? adc off ? wdt ena ? le 1.5 ? .0 a 5v ? .0 6.0 a i idle1 idle1 mode stand ?? c ??? ent (hxt ? erc ? hirc) ? v no load ? adc off ? wdt ena ? le ? f sys = 1 ? mhz on 0.55 0.8 ? ma 5v 1. ? 0 ? .00 ma i sleep0 sleep0 mode stand ?? c ??? ent (lxt and lirc off) ? v no load ? adc off ? wdt disa ? le 1 a 5v ? a i sleep1 sleep1 mode stand ?? c ??? ent (lxt o ? lirc on) ? v no load ? adc off ? wdt ena ? le 1.5 ? .0 a 5v ? .5 5.0 a v il1 inp ? t low voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0 0. ? v dd v v ih1 inp ? t high voltage fo ? i/o po ? ts o ? inp ? t pins except res pin 0.7v dd v dd v v il ? inp ? t low voltage ( res) 0 0.4v dd v v ih ? inp ? t high voltage ( res) 0.9v dd v dd v v lvr lvr voltage level lvr ena ? le ? ? .10v -5% ? .1 +5% v lvr ena ? le ? ? .55v -5% ? .55 +5% v lvr ena ? le ? ? .15v -5% ? .15 +5% v lvr ena ? le ? 4. ? 0v -5% 4. ? 0 +5% v v lvd lvd voltage level lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .4v -5% ? .40 +5% v lvden=1 ? v lvd = ? .7v -5% ? .70 +5% v lvden=1 ? v lvd = ? .0v -5% ? .00 +5% v lvden=1 ? v lvd = ? . ? v -5% ? . ? 0 +5% v lvden=1 ? v lvd = ? .6v -5% ? .60 +5% v lvden=1 ? v lvd =4.4v -5% 4.4 +5% v i lv additional powe ? cons ? mption if lvr and lvd is used lvr ena ? le ? lvden=0 60 90 a lvr disa ? le ? lvden=1 75 115 a lvr ena ? le ? lvden=1 90 1 ? 5 a v ol o ? tp ? t low voltage i/o po ? t ? v i ol =9ma 0. ? v 5v i ol = ? 0ma 0.5 v
rev. 1.90 ?4 ?e???a?? 18? ?01? rev. 1.90 ? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions v oh o ? tp ? t high voltage i/o po ? t ? v i oh = - ? . ? ma ? .7 v 5v i oh =-7.4ma 4.5 v r ph p ? ll-high resistance fo ? i/o po ? ts ? v ? 0 60 100 k 5v 10 ? 0 50 k i scom scom ope ? ating c ??? ent 5v scomc ? isel[1:0]=00 17.5 ? 5.0 ?? .5 a scomc ? isel[1:0]=01 ? 5 50 65 a scomc ? isel[1:0]=10 70 100 1 ? 0 a scomc ? isel[1:0]=11 140 ? 00 ? 60 a v scom v dd / ? voltage fo ? lcd com 5v no load 0.475 0.500 0.5 ? 5 v dd v 1 ? 5 1. ? 5v refe ? ence with b ? ffe ? voltage - ? % 1. ? 5 + ? % v i 1 ? 5 additional powe ? cons ? mption if 1. ? 5v refe ? ence with b ? ffe ? is ? sed ? 00 ? 00 a a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? . ? v~5.5v dc 8 mhz ? .7v~5.5v dc 1 ? mhz 4.5v~5.5v dc ? 0 mhz f sys s ? stem clock (hxt) ? . ? v~5.5v 0.4 8 mhz ? .7v~5.5v 0.4 1 ? mhz 4.5v~5.5v 0.4 ? 0 mhz f hirc s ? stem clock (hirc) ? v/5v ta= ? 5c - ? % 4 + ? % mhz ? v/5v ta= ? 5c - ? % 8 + ? % mhz 5v ta= ? 5c - ? % 1 ? + ? % mhz ? v/5v ta=0~70c -5% 4 +5% mhz ? v/5v ta=0~70c -4% 8 +4% mhz 5v ta=0~70c -5% 1 ? + ? % mhz ? . ? v~ ? .6v ta=0~70c -7% 4 +7% mhz ? .0v~5.5v ta=0~70c -5% 4 +9% mhz ? . ? v~ ? .6v ta=0~70c -6% 8 +4% mhz ? .0v~5.5v ta=0~70c -4% 8 +9% mhz ? .0v~5.5v ta=0~70c -6% 1 ? +7% mhz ? . ? v~ ? .6v ta=-40c~85c -1 ? % 4 +8% mhz ? .0v~5.5v ta=-40c~85c -10% 4 +9% mhz ? . ? v~ ? .6v ta=-40c~85c -15% 8 +4% mhz ? .0v~5.5v ta=-40c~85c -8% 8 +9% mhz ? .0v~5.5v ta=-40c~85c -1 ? % 1 ? +7% mhz f erc s ? stem clock (erc) 5v ta= ? 5c ? r=120k* - ? % 8 + ? % mhz 5v ta=0c~70c, r=120k* -5% 8 +6% mhz 5v ta=-40c~85c, r=120k* -7% 8 +9% mhz ? .0v~5.5v ta=-40c~85c, r=120k* -9% 8 +10% mhz ? . ? v~5.5v ta=-40c~85c, r=120k* -15% 8 +10% mhz f lxt s ? stem clock (lxt) ?? .768 khz
rev. 1.90 ? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions f lirc s ? stem clock (lirc) 5v ta= ? 5c -10% ?? +10% khz ? . ? v~5.5v ta=-40c~85c -50% ?? +60% khz f timer time ? inp ? t pin ?? eq ? enc ? 1 f sys t res exte ? nal reset low p ? lse width 1 s t int inte ??? pt p ? lse width 1 t sys t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to inte ??? pt ? 0 45 90 s t lvds lvdo sta ? le time 15 s t bgs v bg t ?? n on sta ? le t ime ? 00 s t eerd eeprom read time 45 90 s t eewr eeprom w ? ite t ime ? 4 ms t sst s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om halt) f sys =hxt o ? lxt 10 ? 4 t sys f sys =erc o ? hirc 15~16 f sys =lirc 1~ ? 1rwh w sys i sys u i d h uhu ohudh oo hh h iuhh d suh uhu uhhh dd h dud i h hudo oodu iuhh d hso dsdu o h hh hhh d d odh d oh h hyh d soh a/d converter characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d conve ? te ? ope ? ating voltage ? .7 5.5 v v adi a/d conve ? te ? inp ? t voltage 0 vre ? v v re ? a/d conve ? te ? refe ? ence voltage ? av dd v dnl diffe ? ential non-linea ? it ? 5v t ad =1.0s 1 ? lsb inl integ ? al non-linea ? it ? 5v t ad =1.0s ? 4 lsb i adc additional powe ? cons ? mption if a/d conve ? te ? is used ? v no load ? t ad =0.5s 0.90 1. ? 5 ma 5v no load ? t ad =0.5s 1. ? 0 1.80 ma t adck a/d conve ? te ? clock pe ? iod 0.5 10 s t adc a/d conve ? sion time (incl ? de sample and hold time) 1 ? - ? it adc 16 t adck t ads a/d conve ? te ? sampling time 4 t adck t on ? st a/d conve ? te ? on-to-sta ? t time ? s
rev. 1.90 ?6 ?e???a?? 18? ?01? rev. 1.90 ? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom comparator electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v cmp compa ? ato ? ope ? ating voltage ? . ? 5.5 v i cmp compa ? ato ? ope ? ating c ??? ent ? v ? 7 56 a 5v 1 ? 0 ? 00 a v cmpos compa ? ato ? inp ? t offset voltage -10 10 mv v hys h ? ste ? esis width ? 0 40 60 mv v cm compa ? ato ? common mode voltage range v ss v dd -1.4v v a ol compa ? ato ? open loop gain 60 80 db t pd compa ? ato ? response time with 100mv ove ? d ? ive (note) ? 70 560 ns 1rwh 0hdvxuhg zlwk ?rpsdudwru rqh lqsxw slq dw 9 &0 9 dd oh h hu s s ud iu ss u iu dd power-on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ens ?? e powe ? -on reset 100 mv rr vdd v dd raising rate to ens ?? e powe ? -on reset 0.0 ? 5 v/ms t por minim ? m time fo ? v dd sta ? s at v por to ens ?? e powe ? -on reset 1 ms
rev. 1.90 ? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining sche me is im plemented in such a way tha t inst ruction fet ching and inst ruction execution are overla pped, hence inst ructions are ef fectively exec uted in one cycl e, wit h the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the begi nning of the t1 cl ock during whi ch ti me a new inst ruction is fet ched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instructi on cycle. although the fetching and executi on of instructi ons takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.90 ?8 ?e???a?? 18? ?01? rev. 1.90 ? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obta in the ac tual jum p or ca ll addre ss and the n anot her cyc le to ac tually exe cute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for i nstructions, suc h a s "jmp" or "cal l" t hat de mand a j ump t o a non-c onsecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine cal l, inte rrupt or reset, etc ., the mic rocontroller mana ges program cont rol by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next inst ruction, whic h has al ready bee n fet ched during the present inst ruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter porgram counter high byte pcl register ht66 ?? 0 pc9 ? pc8 pcl7~pcl0 ht66 ?? 0 pc10~pc8 ht66 ? 40 pc11~pc8 ht66 ? 50 pc1 ? ~pc8 ht66 ? 60 pc1 ? ~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a sho rt pr ogram ju mp ca n be ex ecuted di rectly, ho wever, as on ly th is lo w by te is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.90 ? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels ht66 ?? 0/ht66 ?? 0 4 ht66 ? 40/ht66 ? 50 8 ht66 ? 60 1 ? arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.90 ?0 ?e???a?? 18? ?01? rev. 1.90 ? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large numbe r of ti mes, al lowing the user the conve nience of code modi fication on the sam e device. by using the appropriate programming tools, these flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 1k14 bits to 12k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity banks ht66 ?? 0 1k14 0 ht66 ?? 0 ? k14 0 ht66 ? 40 4k15 0 ht66 ? 50 8k16 0 ht66 ? 60 1 ? k16 0 ? 1 the ht66f60 has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register .

program memory structure
rev. 1.90 ?? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 0000h is rese rved for use by the devi ce rese t for program ini tialisation. afte r a devi ce rese t is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up th e ta ble po inter, th e ta ble da ta ca n be re trieved fr om th e pro gram mem ory usi ng the "tabrd [m]" or "tabrdl [m]" instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory re gister [m ] as spe cified in th e in struction. th e hi gher or der ta ble da ta by te fr om the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.

rev. 1.90 ?? ?e???a?? 18? ?01? rev. 1.90 ?? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2k program memory of the ht66f30. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "t abrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example: tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; i nitialise low byte table pointer - note that this address ; is referenced mov tblp, a mov a,07h ; initialise high table pointer mov tbhp, a : : tabrdl te mpreg1 ; t ransfers value in table referenced by table pointer data at ; program memory address "706h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl te mpreg2 ; t ransfers value in table referenced by table pointer data at ; program memory address "705h" transferred to tempreg2 and tblh in ; t his example the data "1ah" is transferred to tempreg1 and data ; "0fh" to register tempreg2 : : org 700h ; sets initial address of program memory dc 000ah, 000bh, 000ch, 000dh, 000eh, 000fh, 001ah, 001bh : :
rev. 1.90 ? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom in circuit programming C icp the provision of fla sh ty pe pro gram mem ory pr ovides th e use r wit h a me ans of co nvenient an d easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or up grading th e pro gram at a la ter sta ge. th is e nables p roduct ma nufacturers t o ea sily keep their ma nufactured product s suppli ed wit h the la test program rel eases wit hout rem oval and re-insertion of the device. mcu programming pins function pa0 se ? ial data inp ? t/o ? tp ? t pa ? se ? ial clock res device reset vdd powe ? s ? ppl ? vss g ? o ? nd the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical de tails re garding th e in -circuit pr ogramming of th e de vices ar e be yond th e sco pe of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the pa 0 and pa 2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin pins res pb0 data pa0 clk pa ? programmer and mcu pins
rev. 1.90 ?4 ?e???a?? 18? ?01? rev. 1.90 ? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. her e ar e lo cated re gisters whi ch ar e ne cessary fo r co rrect op eration of th e de vice. man y of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several banks, the structure of which depends upon the device chosen. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. device capacity banks ht66 ?? 0 648 0: 60h~7 ? h 1: 60h~7 ? h ht66 ?? 0 968 0: 60h~7 ? h 1: 60h~7 ? h ? : 60h~7 ? h ht66 ? 40 19 ? 8 0: 80h~ ?? h 1: 80h~b ? h ht66 ? 50 ? 848 0: 80h~ ?? h 1: 80h~ ?? h ? : 80h~ ?? h ht66 ? 60 5768 0: 80h~ ?? h 1: 80h~ ?? h ? : 80h~ ?? h ? : 80h~ ?? h 4: 80h~b ? h
rev. 1.90 ? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.90 ?6 ?e???a?? 18? ?01? rev. 1.90 ? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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? ht66f40 special purpose data memory ht66f50 special purpose data memory
rev. 1.90 ? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.90 ?8 ?e???a?? 18? ?01? rev. 1.90 ? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal regist ers. the me thod of i ndirect addre ssing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from ba nk 0 whi le t he iar1 and mp1 regist er pa ir c an access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory poi nters, kn own as mp0 an d mp1 ar e pr ovided. th ese mem ory poi nters ar e physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data fro m a ll ba nks a ccording to b p re gister. di rect addre ssing ca n onl y b e use d wi th ba nk 0, all other banks must be addressed indirectly using mp1 and iar1. note that for the ht66f20 and ht66f30 devices, bit 7 of the memory pointers is not required to address the full memory space. when bit 7 of the memory pointers for ht66f20 and ht66f30 devices is read, a value of "1" will be returned. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4.
rev. 1.90 40 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 41 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 0 0h start: mov a,04h ; setup size of block mov block,a mov a, offset adre s1 ; ac cumulator lo aded wi th fr st ra m add ress mov mp 0,a ; se tup me mory poi nter wit h fr st ra m ad dress loop: clr ia r0 ; cl ear th e da ta at add ress de fned by mp 0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: 7kh ld l h khh l kd l kh hdh k deh hhhfh l dh hflf 50 dhh bank pointer C bp hshqglqj xsrq zklfk ghylfh lv xvhg wkh 3urjudp dqg dwd 0hpru duh glylghg lqwr vhyhudo edqnv 6hohfwlqj wkh uhtxluhg 3urjudp dqg dwd 0hpru duhd lv dfklhyhg xvlqj wkh %dqn 3rlqwhu %lw ri wkh %dqn 3rlqwhu lv xvhg wr vhohfw 3urjudp 0hpru %dqn ru zkloh elwv a duh xvhg wr vhohfw dwd 0hpru %dqnv a 7kh dwd 0hpru lv lqlwldolv hg wr %dqn diwhu d uhv hw h[fhsw iru d :7 wlphrxw uhvhw lq wkh 3 rzhu rzq 0rgh lq zklfk fdvh wkh dwd 0hpru edqn uhpdlqv xqdiihfwhg ,w vkrxog eh qrwhg wkdw wkh 6shfldo )xqfwlrq dwd 0hpru lv qrw diihfwhg e wkh edqn vhohfwlrq zklfk phdqv wkdw wkh 6shfldo )xqfwlrq 5hjlvw huv fdq eh dffh vvhg iurp zlwkl q dq edqn luhfw o dgguhvvl qj wkh dwd 0hpru zloo dozdv uhvxow lq %dqn ehlqj dffhvvhg luuhvshfwlyh ri wkh ydoxh ri wkh %dqn 3rlqwhu ffhvvlqj gdwd iurp edqnv rwkhu wkdq %dqn pxvw eh lpsohphqwhg xvlqj ,qgluhfw dgguhvvlqj v erwk wkh 3urjudp 0hpru dqg dwd 0hpru vkduh wkh vdph %dqn 3rlqwhu 5hjlvwhu fduh pxvw eh wdnhq gxulqj surjudpplqj device bit 7 6 5 4 3 2 1 0 ht66 ?? 0 ht66 ? 40 dmbp0 ht66 ?? 0 ht66 ? 50 dmbp1 dmbp0 ht66 ? 60 pmbp0 dmbp ? dmbp1 dmbp0 bp register list
rev. 1.90 40 ?e???a?? 18? ?01? rev. 1.90 41 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bp register ? ht66f20/ht66f40 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 %lw a 8qlpsohphqwhg uhdg dv %lw dmbp0 6hohfw dwd 0hpru dnv dn dn ? ht66f30/ht66f50 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 %lw a 8qlpsohphqwhg uhdg dv %lw a dmbp1, dmbp0 6hohfw dwd 0hpru dnv dn dn dn 8ghhg ? ht66f60 bit 7 6 5 4 3 2 1 0 name pmbp0 dmbp ? dmbp1 dmbp0 r/w r/w r/w r/w r/w por 0 0 0 0 %lw a 8qlpsohphqwhg uhdg dv %lw pmbp0 6hohfw 3urudp 0hpru dnv dn 3urudp 0hpru gguhvv lv iurp dn 3urudp 0hpru gguhvv lv iurp lw 8lpsohphwhg uhdg dv lw dmbp2~dmbp0 6hohfw dwd 0hpru dnv dn dn dn dn dn 8ghhg
rev. 1.90 4 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 4? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logic al opera tion such as addit ion, subtrac tion, shift , etc ., to the dat a mem ory resulting in higher programm ing and tim ing overheads. data tra nsfer operations usually invol ve the temporary stora ge funct ion of the acc umulator; for ex ample, when tra nsferring dat a bet ween one user defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program mem ory. tbl p and tbhp are the ta ble point er and indi cates the loc ation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.90 4? ?e???a?? 18? ?01? rev. 1.90 4 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power -up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.90 44 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 45 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name to pd ? ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x: ? nknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out fag 0: after power up or executing the clr wdt or hal t instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.90 44 ?e???a?? 18? ?01? rev. 1.90 45 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically era sable program mable rea d only mem ory, is by it s nat ure a non-vola tile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application poss ibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity varies from 328 to 2568 bits, according to the device selected. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ht66 ?? 0 ?? 8 00h~1 ? h ht66 ?? 0 648 00h~ ?? h ht66 ? 40 1 ? 88 00h~7 ? h ht66 ? 50/ht66 ? 60 ? 568 00h~ ?? h eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register however, being located in bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed.
rev. 1.90 46 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 47 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom eeprom register list ? ht66f20 name bit 7 6 5 4 3 2 1 0 eea d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd ? ht66f30 name bit 7 6 5 4 3 2 1 0 eea d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd ? ht66f40 name bit 7 6 5 4 3 2 1 0 eea d6 d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd ? ht66f50/ht66f60 name bit 7 6 5 4 3 2 1 0 eea d7 d6 d5 d4 d ? d ? d1 d0 eed d7 d6 d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register ? ht66f20 bit 7 6 5 4 3 2 1 0 name d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por "x" ? nknown bit 7~5 unimplemented, read as "0" bit 4~0 data eeprom address data eeprom address bit 4~bit 0
rev. 1.90 46 ?e???a?? 18? ?01? rev. 1.90 47 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f30 bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por "x" ? nknown bit 7~6 unimplemented, read as "0" bit 5~0 data eeprom address data eeprom address bit 5~bit 0 ? ht66f40 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por "x" ? nknown bit 7 unimplemented, read as "0" bit 6~0 data eeprom address data eeprom address bit 6~bit 0 ? ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por "x" ? nknown bit 7~0 data eeprom address data eeprom address bit 7~bit 0
rev. 1.90 48 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 49 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eepro m write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the dat a ee prom wr ite co ntrol bi t an d whe n set hi gh by th e ap plication program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to "1" at the same time in one instruction. thewrand rd can not be set to "1" at the same time.
rev. 1.90 48 ?e???a?? 18? ?01? rev. 1.90 49 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom reading data from the eeprom to read data from the eepro m, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is exe cuted. the app lication prog ram ca n pol l the rd bit to det ermine when th e dat a is valid for reading. writing data to the eeprom to write data to the ee prom, the wri te ena ble bit , wre n, in the ee c regi ster must frst be set high to enable the write function. the eepro m address of the data to be written must then be placed in the eea register and the data placed in the eed register. if thewrbit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be im plemented ei ther by poll ing the wr bit in the ee c regi ster or by using the eeprom interrupt. wh en th e wri te cy cle te rminates, th e wr bi t wil l be au tomatically cl eared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on thewrite enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. howeve r as the ee prom is cont ained wit hin a mult i-function inte rrupt, the assoc iated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request flag will both be set. if the global, eepro m and multi-function interrupts are enabled and the stack is not full, a jump to the associated mult i-function inte rrupt vec tor wil l ta ke pla ce. whe n the int errupt is servi ced only the multi-function interrupt fag will be automatic ally reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.90 50 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 51 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. programming examples reading data from the eeprom C polling mothod mov a, eep rom_adres ; us er de fned add ress mov eea, a mov a, 040h ; set up me mory poi nter mp 1 mov mp1, a ; m p1 po ints to ee c re gister mov a, 01h ; set up ba nk poi nter mov bp, a set iar1.1 ; se t rd en bit , en able re ad op erations set iar1.0 ; st art rea d cy cle - set rd bi t back: sz iar1.0 ; ch eck fo r read cy cle end jmp back clr iar1 ; di sable eep rom read /write clr bp mov a, eedata ; mo ve r ead dat a to r egister mov read_data, a writing data to the eeprom C polling mothod mov a, eep rom_adres ; us er de fned add ress mov eea, a mov a, eeprom_data ; us er def ned dat a mov eed, a mov a, 040h ; set up me mory poi nter mp 1 mov mp1, a ; m p1 po ints to ee c re gister mov a, 01h ; set up ba nk poi nter mov bp, a set iar1.3 ; se t wr en bit , en able wr ite op erations set iar1.2 ; sta rt wr ite cy cle - se t wr bit set emi back: sz iar1.2 ; ch eck fo r wri te cy cle end jmp back clr iar1 ; di sable eep rom read /write clr bp
rev. 1.90 50 ?e???a?? 18? ?01? rev. 1.90 51 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for thewatchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide rang e of bot h fast and slow syste m osci llators. all osci llator opt ions are selected th rough th e co nfiguration opt ions. th e high er fre quency osc illators pro vide high er performance bu t ca rry wit h it th e di sadvantage of hi gher po wer re quirements, whi le th e op posite is of course true for the lower frequency oscillators. wi th the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? nal c ?? stal hxt 400khz~ ? 0mhz osc1/osc ? exte ? nal rc erc 8mhz osc1 inte ? nal high speed rc hirc 4 ? 8 o ? 1 ? mhz exte ? nal low speed c ?? stal lxt ?? .768khz xt1/xt ? inte ? nal low speed rc lirc ?? khz oscillator types system clock confgurations there are fve methods of generating the system clock, three high speed oscillators and two low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator, external rc network oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow spee d or high spee d system cloc k is also determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
rev. 1.90 5 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 5? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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rev. 1.90 5? ?e???a?? 18? ?01? rev. 1.90 5 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom external crystal/ceramic oscillator C hxt the external crysta l/ceramic syste m osci llator is one of the high freque ncy osci llator choi ces, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacture r s specifcation.
? ? ?? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0p ? 0p ? 8mhz 0p ? 0p ? 4mhz 0p ? 0p ? 1mhz 100p ? 100p ? note: c1 and c ? val ? es a ? e fo ? g ? idance onl ? . crystal recommended capacitor values
rev. 1.90 54 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 55 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m is connected between osc1 and vdd , and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation freque ncy; the ext ernal ca pacitor has no infue nce over the freque ncy and is conne cted for stability purposes only. device trimming during the manufacturing process and the inclusion of internal fr equency co mpensation ci rcuits ar e use d to en sure th at th e in fluence of th e po wer supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v volt age power supply and te mperature of 25?c degre es, the osci llator wil l have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. external rc oscillator C erc internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc osc illator ha s th ree fxe d fr equencies of ei ther 4mhz , 8mhz or 12 mhz. dev ice trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins.
rev. 1.90 54 ?e???a?? 18? ?01? rev. 1.90 55 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications whe re pre cise fre quencies ar e esse ntial, th ese co mponents ma y be re quired to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller ac tivity and to conse rve power . howeve r, in ma ny mi crocontroller appl ications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacture r s specificati on. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins.
? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 ?? .768khz 10p ? 10p ? note: 1. c1 and c ? val ? es a ? e fo ? g ? idance onl ? . ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.90 56 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 57 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register . lxtlp bit lxt mode 0 q ? ick sta ? t 1 low-powe ? after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mo de by set ting th e lxt lp bi t hi gh. th e osc illator wil l co ntinue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power -on. it should be not ed tha t, no ma tter what con dition the lxt lp bit is set to, the lxt osci llator wil l always function normally, the only difference is that it will take more time to start up if in the low-power mode. internal low speed oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, re quiring no ex ternal co mponents fo r it s im plementation. dev ice tr imming du ring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillators the low spee d osci llators, in add ition to provi ding a syste m cl ock sourc e are al so used to provi de a clock source to two ot her de vice fu nctions. th ese ar e th e wa tchdog ti mer an d th e ti me ba se interrupts.
rev. 1.90 56 ?e???a?? 18? ?01? rev. 1.90 57 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom operating modes and system clocks present day applicati ons require that their microcontrol lers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powere d port able appl ications. the fast cl ocks requi red for high perform ance wil l by their nature inc rease cur rent con sumption and of cou rse vic e-versa, lowe r spee d cl ocks red uce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clock the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main syst em cl ock, ca n co me fr om ei ther a hi gh fr equency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~ck s0 bits in the smo d register . the high speed system clock can be sourced from either an hxt, erc or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base cl ock, f tbc . each of these int ernal cl ocks are source d by ei ther the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. together with f sys /4 it is also used as one of the clock sources for the watchdog timer. the ftbc clock is used as a source for the time base interrupt functions and for the tms.
rev. 1.90 58 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 59 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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?? ? ?? ? ?? ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.90 58 ?e???a?? 18? ?01? rev. 1.90 59 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the applicat ion. there are two modes allowi ng normal operation of the microcontroller, the normal mode and slow mode. the rem aining four mode s, the sle ep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f s f tbc normal mode on f h ~f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off ? normal mode as the name sugg ests th is is on e of th e ma in op erating mo des whe re th e mi crocontroller ha s all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillat or is used, running the microcontrolle r at a divided clock ratio reduces the operating current. ? slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. ? sleep0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to 0 . if the l vden is set to "1", it wo n t enter the sleep0 mode. ? sleep1 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is "1" or the watchdog timer function is enabled and if its clock source is chosen via confguration option to come from the f sub .
rev. 1.90 60 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 61 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit i n t he wdt c regist er i s low . in t he idl e0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer , tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4 then the f s clock will be off, and if the source comes from f sub then f s will be on. ? idle1 mode the idle1 mod e is en tered whe n an halt in struction is ex ecuted an d whe n th e idl en bi t in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer , tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed sys tem oscillator. in the idle1 mode the watchdog timer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. control register a single register , smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 ? sten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wa ke-up co ntrol bi t whi ch de termines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available.
rev. 1.90 60 ?e???a?? 18? ?01? rev. 1.90 61 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will en ter th e idl e mod e. in th e idl e1 mod e th e cpu wil l stop run ning but the system cl ock wil l cont inue to kee p the peri pheral func tions ope rational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power.
rev. 1.90 6 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 6? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the devi ce is up and running as fast as possibl e a fast wa ke-up funct ion is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fastwake-up function has no effect because the f sub clock is stopped. the fast wake-up ena ble/disable funct ion is cont rolled using the fsten bit in the smod register. if the hxt oscilla tor is select ed as the normal mode system cloc k, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator . if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no ef fect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10 ? 4 hxt c ? cles 10 ? 4 hxt c ? cles 1~ ? hxt c ? cles 1 10 ? 4 hxt c ? cles 1~ ? f sub c ? cles (s ? stem ?? ns with f sub frst for 1024 hxt cycles and then switches ove ? to ?? n with the hxt clock ) 1~ ? hxt c ? cles erc x 15~16 erc c ? cles 15~16 erc c ? cles 1~ ? erc c ? cles hirc x 15~16 hirc c ? cles 15~16 hirc c ? cles 1~ ? hirc c ? cles lirc x 1~ ? lirc c ? cles 1~ ? lirc c ? cles 1~ ? lirc c ? cles lxt x 10 ? 4 lxt c ? cles 10 ? 4 lxt c ? cles 1~ ? lxt c ? cles wake-up times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode.
rev. 1.90 6? ?e???a?? 18? ?01? rev. 1.90 6 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom operating mode switching the device can swit ch betwe en operati ng modes dynami cally all owing the user to sel ect the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes.

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rev. 1.90 64 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 65 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom normal mode to slow mode switching when running in th e normal mod e, whi ch use s the hi gh spe ed syst em osc illator, an d th erefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscilla tors and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lt o bit in the smod register.
? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ?
rev. 1.90 64 ?e???a?? 18? ?01? rev. 1.90 65 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110", or "111". as a certain amount of time will be required for the high frequency clock to stabilis e, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ?
rev. 1.90 66 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 67 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and time base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or lvd on. whe n thi s inst ruction is exe cuted under the condi tions desc ribed above , the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the halt instruction, but the wdt or l vd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in th e ap plication pr ogram wit h th e idl en bi t in smod re gister eq ual to 1 an d th e fsyson bit in wdtc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.90 66 ?e???a?? 18? ?01? rev. 1.90 67 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in th e ap plication pr ogram wit h th e idl en bi t in smod re gister eq ual to 1 an d th e fsyson bit in wdtc register equal to 1. when this instruction is executed under the with conditions described above, the following will occur: ? the system clock and time base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleare d and resume counting if the wdt is enabled regardle ss of the wdt clock source which originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, the re are othe r consi derations whic h must al so be ta ken int o ac count by the ci rcuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.90 68 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 69 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pa wu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execut ion at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before ente ring the sleep or idle mode, the wake -up functi on of the rela ted interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1" at this time, the lxt osc illator ma y no t be sta bility if f sub is from lxt osc illator. th e sam e sit uation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is "1", the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt, tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub .
rev. 1.90 68 ?e???a?? 18? ?01? rev. 1.90 69 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lxt or lirc oscillators, again chosen via a confguration option. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog timer clock source option is the f sys /4 clock. the watchdog timer clock source can originate from its own internal lirc oscillator, the lxt oscillator or f sys /4. it is divided by a value of 2 8 to 2 15 , using the ws2~ws0 bits in the wdtc register to obtain the required watchdog timer time-out period. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the watchdog timer . wdtc register bit 7 6 5 4 3 2 1 0 name ? syson ws ? ws1 ws0 wdten ? wdten ? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 : f sys control in idle mode 0: disable 1: enable bit 6~4 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit 3~0 : wdt software control 1010: disable other: enable
rev. 1.90 70 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 71 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom watchdog timer operation the watchdog ti mer opera tes by providi ng a devi ce reset when it s ti mer overfows. thi s me ans that in the application progra m and duri ng norm al opera tion the user has to stra tegically cl ear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. some of the watchdog timer options, such as enable/disable, clock source selection and clear instruction type are selected using confguration options. in addition to a confguration option to enable/disable the watchdog timer, there are also four bits, wdten3~wdten0, in the wdtc register to offer an additional enable/disable co ntrol of th e wa tchdog ti mer. to di sable th e wa tchdog ti mer, as wel l as the confguration option being set to disable, the wdten3~wdten0 bits must also be set to a specifc value of "1010" . any other values for these bits will keep the watchdog timer enabled, irrespective of the confguration enable/disable setting. after power on these bits will have the value of 1010. if the watchdog ti mer is used it is rec ommended tha t the y are set to a val ue of 0101 for maximum noise immunity. note that if the watchdog timer has been disabled, then any instruction relating to its operation will result in no operation. wdt confguration option wdten3~wdten0 bits wdt wdt ena ? le ena ? le wdt disa ? le except 1010 ena ? le wdt disa ? le 1010 disa ? le watchdog timer enable/disable control under normal program opera tion, a wa tchdog ti mer ti me-out wil l ini tialise a devi ce rese t and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer . the frst is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a hal t instruction. there are two methods of using software instructions to clear thewatchdog timer , one of which mus t be c hosen by c onfguration opt ion. the frst opt ion i s t o use t he si ngle "cl r wdt " i nstruction whi le the second is to use the two com mands "cl r wdt 1" and "cl r wdt 2". for the frst opt ion, a simple execution of "clr wdt" will clear the wdt while for the second option, both "clr wdt1" and "clr wdt2" must both be executed alte rnately to successful ly clea r the wat chdog tim er. note that for this second option, if "clr wdt1" is used to clear the watchdog timer , successive executions of this instruction will have no effect, only the execution of a "clr wdt2" instruction will clear the watchdog timer . similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the watchdog timer . the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the watchdog timer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended.
rev. 1.90 70 ?e???a?? 18? ?01? rev. 1.90 71 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

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? ? ? ? -? -? ?? ? ? ? ? ? ? ? ? ? ?? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller , after a short delay , will be in a well defined state and ready to execute the frst pr ogram in struction. aft er th is po wer-on re set, ce rtain im portant in ternal re gisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to th e po wer-on re set, sit uations ma y ar ise whe re it is ne cessary to for cefully ap ply a reset condition when the microcontroller is running. one example of this is where after power has been applied and th e mi crocontroller is al ready runn ing, th e res line is forcefully pul led lo w. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=100ms power-on reset timing chart
rev. 1.90 7 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 7? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? res pin as the reset pin is share d wit h pb.0, the rese t funct ion must be sel ected using a confgura tion option. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc ne twork is co nnected to th e res pin, whose ad ditional ti me de lay wil l en sure th at th e res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer . for most applications a resi stor conne cted bet ween vdd and the res pin and a ca pacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operat e within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environm ents where power line noise is signifcant. extern res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=100ms res reset timing chart
rev. 1.90 7? ?e???a?? 18? ?01? rev. 1.90 7 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom when the reset pi n is dr iven lo w by ex ternal ha rdware, mo st of th e mi crocontroller pi ns wil l be forced into a high impedance condition. however special attention must be made to the pa5/c1x/ sdo/an5 and pb2/osc2 pins as these two pins will be forced into a logical output low condition when the reset pin is held low. for this reason it is recommended that these two pins are not connected to low impedance sources in the application circuit to eliminate the possibility of two low impedance sources being connected together. this situation only occurs when the reset pin is pulled low by external hardware and not during a power on or other reset type. pin name pin status pa5/c1x/sdo/an5 o ? tp ? t low pb ? /osc ? o ? tp ? t low othe ? pins high impedance ? low voltage reset C l vr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lv r includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected using confguration options. note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart ? watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to 1. note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart ? watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt . the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart
rev. 1.90 74 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 75 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, suc h as th e sle ep or idl e mod e fu nction or wa tchdog ti mer. th e re set fl ags ar e shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset ? ? res o ? lvr ? eset d ?? ing normal o ? slow mode ope ? ation 1 ? wdt time-o ? t ? eset d ?? ing normal o ? slow mode ope ? ation 1 1 wdt time-o ? t ? eset d ?? ing idle o ? sleep mode ope ? ation ? stands fo ? ? nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am co ? nte ? reset to ze ? o inte ??? pts all inte ??? pts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins co ? nting time ? /event co ? nte ? time ? co ? nte ? will ? e t ?? ned off inp ? t/o ? tp ? t po ? ts i/o po ? ts will ? e set ? p as inp ? ts ? and an0~an11 in as a/d inp ? t pin stack pointe ? stack pointe ? will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. ht66f20 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 ??? ???? mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 ??? ???? bp - - - - - - -0 - - - - - - -0 - - - - - - -0 - - - - - - - ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh - - xx xxxx - - ?? ???? - - ?? ???? - - ?? ???? tbhp - - - - - -xx - - - - - - ?? - - - - - - ?? - - - - - - ?? status - -00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? integ - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i0 - -00 - -00 - -00 - -00 - -00 - -00 - - ?? - - ??
rev. 1.90 74 ?e???a?? 18? ?01? rev. 1.90 75 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) m ? i1 - -00 - -00 - -00 - -00 - -00 - -00 - - ?? - - ?? m ? i ? 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu - - 00 0000 - - 00 0000 - - 00 0000 - - ?? ???? pb - - 11 1111 - - 11 1111 - - 11 1111 - - ?? ???? pbc - - 11 1111 - - 11 1111 - - 11 1111 - - ?? ???? pcpu - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? pc - - - - 1111 - - - - 1111 - - - - 1111 - - - - ???? pcc - - - - 1111 - - - - 1111 - - - - 1111 - - - - ???? adrl(adre ? =0) xxxx - - - - xxxx - - - - xxxx - - - - ???? - - - - adrl(adre ? =1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =1) - - - - xxxx - - - - xxxx - - - - xxxx - - - - ???? adcr0 0110 - 000 0110 - 000 0110 - 000 ???? - ??? adcr1 00 -0 - 000 00 -0 - 000 00 -0 - 000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? cp1c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? simc0 1110 000 - 1110 000 - 1110 000 - ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? eea - - - x xxxx - - - x xxxx - - - x xxxx - - - 0 0000 eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? tmpc0 - - 01 - - - 1 - - 01 - - - 1 - - 01 - - - 1 - - ?? - - - ? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: "u" stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.90 76 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 77 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f30 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 ??? ???? mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1 ??? ???? bp - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh - - xx xxxx - - ?? ???? - - ?? ???? - - ?? ???? tbhp - - - - - xxx - - - - - ??? - - - - - ??? - - - - - ??? status - -00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? integ - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i0 - -00 - -00 - -00 - -00 - -00 - -00 - - ?? - - ?? m ? i1 - 000 - 000 - 000 - 000 - 000 -000 - ??? - ??? m ? i ? 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu - - 00 0000 - - 00 0000 - - 00 0000 - - ?? ???? pb - - 11 1111 - - 11 1111 - - 11 1111 - - ?? ???? pbc - - 11 1111 - - 11 1111 - - 11 1111 - - ?? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? adrl(adre ? =0) xxxx - - - - xxxx - - - - xxxx - - - - ???? - - - - adrl(adre ? =1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =1) - - - - xxxx - - - - xxxx - - - - xxxx - - - - ???? adcr0 0110 - 000 0110 - 000 0110 - 000 ???? - ??? adcr1 00 -0 - 000 00 -0 - 000 00 -0 - 000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? cp1c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? simc0 1110 000 - 1110 000 - 1110 000 - ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ????
rev. 1.90 76 ?e???a?? 18? ?01? rev. 1.90 77 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm0dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? eea - - xx xxxx - - xx xxxx - - xx xxxx - - ?? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? tmpc0 1 - 01 - - 01 1 - 01 - - 01 1 - 01 - - 01 ? - ?? - - ?? prm0 - - - - - 000 - - - - - 000 - - - - - 000 - - - - - ??? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: "u" stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.90 78 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 79 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f40 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp - - - - - - -0 - - - - - - -0 - - - - - - -0 - - - - - - - ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh - xxx xxxx - ??? ???? - ??? ???? - ??? ???? tbhp - - - - xxxx - - - - ???? - - - - ???? - - - - ???? status - -00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? integ - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i0 0000 0000 0000 0000 0000 0000 ???? ???? m ? i1 - 000 - 000 - 000 - 000 - 000 - 000 - ??? - ??? m ? i ? 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 ???? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? pdpu 0000 0000 0000 0000 0000 0000 ???? ???? pd 1111 1111 1111 1111 1111 1111 ???? ???? pdc 1111 1111 1111 1111 1111 1111 ???? ???? pepu 0000 0000 0000 0000 0000 0000 ???? ???? pe 1111 1111 1111 1111 1111 1111 ???? ???? pec 1111 1111 1111 1111 1111 1111 ???? ???? p ? pu - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? p ? - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? p ? c - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? adrl(adre ? =0) xxxx - - - - xxxx - - - - xxxx - - - - ???? - - - - adrl(adre ? =1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =1) - - - - xxxx - - - - xxxx - - - - xxxx - - - - ???? adcr0 0110 - 000 0110 - 000 0110 - 000 ???? - ??? adcr1 00 -0 - 000 00 -0 - 000 00 -0 - 000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ????
rev. 1.90 78 ?e???a?? 18? ?01? rev. 1.90 79 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) cp0c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? cp1c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? simc0 1110 000 - 1110 000 - 1110 000 - ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? eea - xxx xxxx - xxx xxxx - xxx xxxx - ??? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? tmpc0 1001 - - 01 1001 - - 01 1001 - - 01 ???? - - ?? tmpc1 - - - - - - 01 - - - - - - 01 - - - - - - 01 - - - - - - ?? prm0 - 0- 0 0000 - 0- 0 0000 - 0- 0 0000 - ? - ? ???? prm1 000 - 0000 000 - 0000 000 - 0000 ??? - ???? prm ? - -00 0000 - -00 0000 - -00 0000 - - ?? ???? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm ? c0 0000 0 - - - 0000 0 - - - 0000 0 - - - ???? ? - - - tm ? c1 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dl 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dh 0000 0000 0000 0000 0000 0000 ???? ???? tm ? al 0000 0000 0000 0000 0000 0000 ???? ???? tm ? ah 0000 0000 0000 0000 0000 0000 ???? ???? tm ? rp 0000 0000 0000 0000 0000 0000 ???? ???? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: "u" stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.90 80 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 81 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f50 register reset (power-on) res or lvr reset wdt time-out (normal operation wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp - - -x xxxx - - - ? ???? - - - ? ???? - - - ? ???? status - -00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? integ - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i0 0000 0000 0000 0000 0000 0000 ???? ???? m ? i1 - 000 - 000 - 000 - 000 - 000 - 000 - ??? - ??? m ? i ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i ? - -00 - -00 - -00 - -00 - -00 - -00 - - ?? - - ?? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 ???? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? pdpu 0000 0000 0000 0000 0000 0000 ???? ???? pd 1111 1111 1111 1111 1111 1111 ???? ???? pdc 1111 1111 1111 1111 1111 1111 ???? ???? pepu 0000 0000 0000 0000 0000 0000 ???? ???? pe 1111 1111 1111 1111 1111 1111 ???? ???? pec 1111 1111 1111 1111 1111 1111 ???? ???? p ? pu - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? p ? - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? p ? c - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? adrl(adre ? =0) xxxx - - - - xxxx - - - - xxxx - - - - ???? - - - - adrl(adre ? =1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =1) - - - - xxxx - - - - xxxx - - - - xxxx - - - - ???? adcr0 0110 - 000 0110 - 000 0110 - 000 ???? - ??? adcr1 00 -0 - 000 00 -0 - 000 00 -0 - 000 ?? - ? - ???
rev. 1.90 80 ?e???a?? 18? ?01? rev. 1.90 81 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register reset (power-on) res or lvr reset wdt time-out (normal operation wdt time-out (idle) acerl 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? cp1c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? simc0 1110 000 - 1110 000 - 1110 000 - ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? eea xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? tmpc0 1001 - - 01 1001 - - 01 1001 - - 01 ???? - - ?? tmpc1 - - 01 - - 01 - - 01 - - 01 - - 01 - - 01 - - ?? - - ?? prm0 - 0- 0 0000 - 0- 0 0000 - 0- 0 0000 - ? - ? ???? prm1 000 - 0000 000 - 0000 000 - 0000 ??? - ???? prm ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm ? c0 0000 0- - - 0000 0- - - 0000 0- - - ???? ? - - - tm ? c1 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dl 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dh 0000 0000 0000 0000 0000 0000 ???? ???? tm ? al 0000 0000 0000 0000 0000 0000 ???? ???? tm ? ah 0000 0000 0000 0000 0000 0000 ???? ???? tm ? rp 0000 0000 0000 0000 0000 0000 ???? ???? tm ? c0 0000 0000 0000 0000 0000 0000 ???? ???? tm ? c1 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dl 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dh - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? tm ? al 0000 0000 0000 0000 0000 0000 ???? ???? tm ? ah - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: "u" stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.90 8 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 8? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f60 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp - - 0- - 000 - - 0- - 000 - - 0- - 000 - - ? - - ??? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp - - xx xxxx - - ?? ???? - - ?? ???? - - ?? ???? status - -00 xxxx - - ?? ???? - - 1 ? ???? - - 11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - ?? - ??? integ 0000 0000 0000 0000 0000 0000 ???? ???? wdtc 0111 1010 0111 1010 0111 1010 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 - 000 0000 - 000 0000 - 000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? intc ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i0 0000 0000 0000 0000 0000 0000 ???? ???? m ? i1 - 000 - 000 - 000 - 000 - 000 - 000 - ??? - ??? m ? i ? 0000 0000 0000 0000 0000 0000 ???? ???? m ? i ? - -00 - -00 - -00 - -00 - -00 - -00 - - ?? - - ?? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 ???? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? pdpu 0000 0000 0000 0000 0000 0000 ???? ???? pd 1111 1111 1111 1111 1111 1111 ???? ???? pdc 1111 1111 1111 1111 1111 1111 ???? ???? pepu 0000 0000 0000 0000 0000 0000 ???? ???? pe 1111 1111 1111 1111 1111 1111 ???? ???? pec 1111 1111 1111 1111 1111 1111 ???? ???? p ? pu 0000 0000 0000 0000 0000 0000 ???? ???? p ? 1111 1111 1111 1111 1111 1111 ???? ???? p ? c 1111 1111 1111 1111 1111 1111 ???? ???? pgpu - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? pg - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? pgc - - - - - -11 - - - - - -11 - - - - - -11 - - - - - - ?? adrl(adre ? =0) xxxx - - - - xxxx - - - - xxxx - - - - ???? - - - - adrl(adre ? =1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh(adre ? =1) - - - - xxxx - - - - xxxx - - - - xxxx - - - - ????
rev. 1.90 8? ?e???a?? 18? ?01? rev. 1.90 8 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) adcr0 0110 0000 0110 0000 0110 0000 ???? ???? adcr1 00 -0 - 000 00 -0 - 000 00 -0 - 000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? cp0c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? cp1c 1000 0 - -1 1000 0 - -1 1000 0 - -1 ???? ? - - ? simc0 1110 000 - 1110 000 - 1110 000 - ???? ??? - simc1 1000 0001 1000 0001 1000 0001 ???? ???? simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? sima/simc ? 0000 0000 0000 0000 0000 0000 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? eea xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eed xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? eec - - - - 0000 - - - - 0000 - - - - 0000 - - - - ???? tmpc0 1001 - - 01 1001 - - 01 1001 - - 01 ???? - - ?? tmpc1 - - 01 - - 01 - - 01 - - 01 - - 01 - - 01 - - ?? - - ?? prm0 0000 0000 0000 0000 0000 0000 ???? ???? prm1 0000 0000 0000 0000 0000 0000 ???? ???? prm ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh - - - - - - 00 - - - - - - 00 - - - - - - 00 - - - - - - ?? tm ? c0 0000 0- - - 0000 0- - - 0000 0- - - ???? ? - - - tm ? c1 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dl 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dh 0000 0000 0000 0000 0000 0000 ???? ???? tm ? al 0000 0000 0000 0000 0000 0000 ???? ???? tm ? ah 0000 0000 0000 0000 0000 0000 ???? ???? tm ? rp 0000 0000 0000 0000 0000 0000 ???? ???? tm ? c0 0000 0000 0000 0000 0000 0000 ???? ???? tm ? c1 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dl 0000 0000 0000 0000 0000 0000 ???? ???? tm ? dh - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? tm ? al 0000 0000 0000 0000 0000 0000 ???? ???? tm ? ah - - - - - -00 - - - - - -00 - - - - - -00 - - - - - - ?? scomc 0000 0000 0000 0000 0000 0000 ???? ???? note: "u" stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.90 84 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 85 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom input/output ports holtek microcontrollers offe r consi derable fexi bility on the ir i/o ports. wi th the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provi des bidi rectional input /output li nes la beled wit h port nam es pa~pg. the se i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a,[m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o port register list ? ht66f20 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d5 d4 d ? d ? d1 d0 pb d5 d4 d ? d ? d1 d0 pbc d5 d4 d ? d ? d1 d0 pcpu d ? d ? d1 d0 pc d ? d ? d1 d0 pcc d ? d ? d1 d0 ? ht66f30 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d5 d4 d ? d ? d1 d0 pb d5 d4 d ? d ? d1 d0 pbc d5 d4 d ? d ? d1 d0 pcpu d7 d6 d5 d4 d ? d ? d1 d0 pc d7 d6 d5 d4 d ? d ? d1 d0 pcc d7 d6 d5 d4 d ? d ? d1 d0
rev. 1.90 84 ?e???a?? 18? ?01? rev. 1.90 85 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f40/ht66f50 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d7 d6 d5 d4 d ? d ? d1 d0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pcpu d7 d6 d5 d4 d ? d ? d1 d0 pc d7 d6 d5 d4 d ? d ? d1 d0 pcc d7 d6 d5 d4 d ? d ? d1 d0 pdpu d7 d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 pepu d7 d6 d5 d4 d ? d ? d1 d0 pe d7 d6 d5 d4 d ? d ? d1 d0 pec d7 d6 d5 d4 d ? d ? d1 d0 p ? pu d1 d0 p ? d1 d0 p ? c d1 d0
rev. 1.90 86 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 87 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f60 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 pbpu d7 d6 d5 d4 d ? d ? d1 d0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pcpu d7 d6 d5 d4 d ? d ? d1 d0 pc d7 d6 d5 d4 d ? d ? d1 d0 pcc d7 d6 d5 d4 d ? d ? d1 d0 pdpu d7 d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 pepu d7 d6 d5 d4 d ? d ? d1 d0 pe d7 d6 d5 d4 d ? d ? d1 d0 pec d7 d6 d5 d4 d ? d ? d1 d0 p ? pu d7 d6 d5 d4 d ? d ? d1 d0 p ? d7 d6 d5 d4 d ? d ? d1 d0 p ? c d7 d6 d5 d4 d ? d ? d1 d0 pgpu d1 d0 pg d1 d0 pgc d1 d0
rev. 1.90 86 ?e???a?? 18? ?01? rev. 1.90 87 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are sel ected using regi sters papu~pgpu, and are im plemented using wea k pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pcpu register ? ht66f30/ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pdpu register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pepu register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0
rev. 1.90 88 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 89 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pfpu register ? ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port bit 7~bit 0 pull-high control 0: disable 1: enable pbpu register ? ht66f20/ht66f30 bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 pbpu : port b bit 5~bit 0 pull-high control 0: disable 1: enable pcpu register ? ht66f20 bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~0 pcpu : port c bit 3~bit 0 pull-high control 0: disable 1: enable pfpu register ? ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pfpu : port f bit 1~bit 0 pull-high control 0: disable 1: enable
rev. 1.90 88 ?e???a?? 18? ?01? rev. 1.90 89 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pgpu register ? ht66f60 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pgpu : port g bit 1~bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist t o wa ke-up t he m icrocontroller, one of whi ch i s t o c hange t he l ogic c ondition on one of t he port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7~bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac~pgc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1
rev. 1.90 90 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 91 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pbc register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register ? ht66f30/ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pdc register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pec register ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pfc register ? ht66f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7~bit 0 input/output control 0: output 1: input
rev. 1.90 90 ?e???a?? 18? ?01? rev. 1.90 91 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pbc register ? ht66f20/ht66f30 bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 pbc : port b bit 5~bit 0 input/output control 0: output 1: input pcc register ? ht66f20 bit 7 6 5 4 3 2 1 0 name d ? d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~0 pcc : port c bit 3~bit 0 input/output control 0: output 1: input pfc register ? ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pfc : port f bit 1~bit 0 input/output control 0: output 1: input pgc register ? ht66f60 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pgc : port g bit 1~bit 0 input/output control 0: output 1: input
rev. 1.90 9 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 9? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins wit h mul ti-functions, ma ny of the se dif ficulties ca n be overc ome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin functi on is selec ted simult aneously. additionall y there are a series of prm0, prm1 and prm2 registers to establish certain pin functions. pin-remapping registers the l imited num ber of suppl ied pi ns i n a pa ckage c an i mpose re strictions on t he a mount of fu nctions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes . some devices include prm 0, prm 1 or prm 2 registers which can select the functions of certain pins. pin-remapping register list ? ht66f30 register name bit 7 6 5 4 3 2 1 0 prm0 pcprm simps0 pckps ? ht66f40 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps0 c0xps0 pdprm simps1 simps0 pckps prm1 tck ? ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 prm ? tp ? 1ps tp ? 0ps tp1b ? ps tp1aps tp01ps tp00ps ? ht66f50 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps0 c0xps0 pdprm simps1 simps0 pckps prm1 tck ? ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 prm ? tp ? 1ps tp ? 0ps tp ? 1ps tp ? 0ps tp1b ? ps tp1aps tp01ps tp00ps ? ht66f60 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps1 c1xps0 c0xps1 c0xps0 pdprm simps1 simps0 pckps prm1 tck ? ps tck1ps tck0ps int ? ps1 int1ps1 int1ps0 int0ps1 int0ps0 prm ? tp ? 1ps tp ? 0ps tp ? 1ps tp ? 0ps tp1b ? ps tp1aps tp01ps tp00ps
rev. 1.90 9? ?e???a?? 18? ?01? rev. 1.90 9 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm0 register ? ht66f30 bit 7 6 5 4 3 2 1 0 name pcprm simps0 pckps r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 pcprm : pc1~pc0 pin-shared function pin remapping control 0: no change 1: tp1b_0 on pc0 change to p a6, tp1b_1 on pc1 change to p a7 if simps0=1 bit 1 simps0 : sim pin remapping control 0: sdo on pa5; sdi/sda on p a6; sck/scl on p a7; scs on pb5 1: sdo on pc1; sdi/sda on pc0; sck/scl on pc7; scs on pc6 bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4 prm0 register ? ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name c1xps0 c0xps0 pdprm simps1 simps0 pckps r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 c1xps0 : c1x pin remapping control 0: c1x on pa5 1: c1x on pf1 bit 5 unimplemented, read as 0 bit 4 c0xps0 : c0x pin remapping control 0: c0x on pa0 1: c0x on pf0 bit 3 pdprm : pd3~pd0 pin-shared function pin remapping control 0: no change 1: tck2 on pd0 change to pb6, tp2_0 on pd1 change to pb7, tck0 on pd2 change to pd6, tck1 on pd3 change to pd7 if simps1, simps0=01 bit 2~1 simps1, simps0 : sim pin remapping control 00: sdo on pa5; sdi/sda on p a6; sck/scl on p a7; scs on pb5 01: sdo on pd3; sdi/sda on pd2; sck/scl on pd1; scs on pd0 10: sdo on pb6; sdi/sda on pb7; sck/scl on pd6; scs on pd7 11: undefned bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4
rev. 1.90 94 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 95 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm0 register ? ht66f60 bit 7 6 5 4 3 2 1 0 name c1xps1 c1xps0 c0xps1 c0xps0 pdprm simps1 simps0 pckps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 c1xps1, c1xps0 : c1x pin remapping control 00: c1x on pa5 01: c1x on pf1 10: c1x on pg1 11: undefned bit 5~4 c0xps1, c0xps0 : c0x pin remapping control 00: c0x on pa0 01: c0x on pf0 10: c0x on pg0 11: undefned bit 3 pdprm : pd3~pd0 pin-shared function pin remapping control 0: no change 1: tck2 on pd0 change to pb6, tp2_0 on pd1 change to pb7, tck0 on pd2 change to pd6, tck1 on pd3 change to pd7 if simps1, simps0=01 or 1 1 bit 2~1 simps1, simps0 : sim pin remapping control 00: sdo on pa5; sdi/sda on p a6; sck/scl on p a7; scs on pb5 01: sdo on pd3; sdi/sda on pd2; sck/scl on pd1; scs on pd0 10: sdo on pb6; sdi/sda on pb7; sck/scl on pd6; scs on pd7 11: sdo on pd1; sdi/sda on pd2; sck/scl on pd3; scs on pd0 bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4
rev. 1.90 94 ?e???a?? 18? ?01? rev. 1.90 95 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm1 register ? ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name tck ? ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pd0 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on p a4 1: tck1 on pd3 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on p a2 1: tck0 on pd2 bit 4 unimplemented, read as 0 bit 3~2 int1ps1, int1ps0 : int1 pin remapping control 00: int1 on pa4 01: int1 on pc5 10: undefned 11: int1 on pe7 bit 1~0 int0ps1, int0ps0 : int0 pin remapping control 00: int0 on pa3 01: int0 on pc4 10: undefned 11: int0 on pe6
rev. 1.90 96 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 97 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm1 register ? ht66f60 bit 7 6 5 4 3 2 1 0 name tck ? ps tck1ps tck0ps int ? ps int1ps1 int1ps0 int0ps1 int0ps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pd0 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on p a4 1: tck1 on pd3 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on p a2 1: tck0 on pd2 bit 4 int2ps : int2 pin remapping control 0: int2 on pc4 1: int2 on pe2 bit 3~2 int1ps1, int1ps0 : int1 pin remapping control 00: int1 on pa4 01: int1 on pc5 10: int1 on pe1 11: int1 on pe7 bit 1~0 int0ps1, int0ps0 : int0 pin remapping control 00: int0 on pa3 01: int0 on pc4 10: int0 on pe0 11: int0 on pe6
rev. 1.90 96 ?e???a?? 18? ?01? rev. 1.90 97 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm2 register ? ht66f40 bit 7 6 5 4 3 2 1 0 name tp ? 1ps tp ? 0ps tp1b ? ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd4 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd1 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pe4 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on p a1 1: tp1a on pc7 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd5 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on p a0 1: tp0_0 on pc6
rev. 1.90 98 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 99 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom prm2 register ? ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name tp ? 1ps tp ? 0ps tp ? 1ps tp ? 0ps tp1b ? ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tp31ps : tp3_1 pin remapping control 0: tp3_1 on pd0 1: tp3_1 on pe3 bit 6 tp30ps : tp3_0 pin remapping control 0: tp3_0 on pd3 1: tp3_0 on pe5 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd4 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd1 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pe4 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on p a1 1: tp1a on pc7 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd5 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on p a0 1: tp0_0 on pc6
rev. 1.90 98 ?e???a?? 18? ?01? rev. 1.90 99 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure

? ?
? ? ? ? - ? ? - ? ?? ? a/d input/output structure
rev. 1.90 100 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 101 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the le vel of whic h depe nds on the othe r conne cted ci rcuitry and whet her pull -high selections have been chosen. if the port control registers, pac~pgc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regist ers, pa~pg, are frst program med. sel ecting which pins are input s and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port ahas the ad ditional ca pability of pr oviding wak e-up fu nctions. wh en th e de vice is in th e sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the nam e tm. the tms are mul ti-purpose ti ming uni ts and serve to provi de operations such as timer/counter , input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three ind ividual int errupts. th e ad dition of inp ut an d ou tput pi ns fo r ea ch tm en sures tha t users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to four tms depending upon which device is selected with each tm having a reference name of tm0, tm1, tm2 and tm3. each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compa ct, sta ndard and enha nced tms wil l be desc ribed in thi s sec tion, the det ailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. function ctm stm etm time ? /co ? nte ? i/p capt ?? e compa ? e match o ? tp ? t pwm channels 1 1 ? single p ? lse o ? tp ? t 1 ? pwm alignment edge edge edge & cent ? e pwm adj ? stment pe ? iod & d ? t ? d ? t ? o ? pe ? iod d ? t ? o ? pe ? iod d ? t ? o ? pe ? iod tm function summary
rev. 1.90 100 ?e???a?? 18? ?01? rev. 1.90 101 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom each device in the series contains a specifc number of either compact type, standard type and enhanced type tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 ht66 ?? 0 10- ? it ctm 10- ? it stm ht66 ?? 0 10- ? it ctm 10- ? it etm ht66 ? 40 10- ? it ctm 10- ? it etm 16- ? it stm ht66 ? 50 10- ? it ctm 10- ? it etm 16- ? it stm 10- ? it ctm ht66 ? 60 10- ? it ctm 10- ? it etm 16- ? it stm 10- ? it ctm tm name/type reference tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count er whose val ue is the n com pared wit h the val ue of pre-progra mmed int ernal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a com pare ma tch sit uation, a tm int errupt signa l wil l be gen erated whic h ca n cl ear the counter and perh aps al so cha nge the con dition of the tm out put pin . the int ernal tm coun ter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock sou rce whi ch dr ives th e ma in co unter in ea ch tm ca n or iginate fr om va rious sou rces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.90 10 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 10? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected usi ng th e tn ck2~tnck0 bi ts. th e tm in put pi n ca n be ch osen to ha ve ei ther a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a com pare ma tch sit uation oc curs. th e ext ernal tpn out put pi n is al so th e pi n where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. asingle bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. all tm output pin names have an "_n" suffx. pin names that include a "_1" or "_2" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm registers ht66 ?? 0 tp0_0 tp1_0 ? tp1_1 tmpc0 ht66 ?? 0 tp0_0 ? tp0_1 tp1a ? tp1b_0 ? tp1b_1 tmpc0 ht66 ? 40 tp0_0 ? tp0_1 tp ? _0 ? tp ? _1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? tmpc0 ? tmpc1 ht66 ? 50 tp0_0 ? tp0_1 tp ? _0 ? tp ? _1 tp ? _0 ? tp ? _1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? tmpc0 ? tmpc1 ht66 ? 60 tp0_0 ? tp0_1 tp ? _0 ? tp ? _1 tp ? _0 ? tp ? _1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? tmpc0 ? tmpc1 tm output pins
rev. 1.90 10? ?e???a?? 18? ?01? rev. 1.90 10 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 ht66 ?? 0 t1cp1 t1cp0 t0cp0 tmpc0 ht66 ?? 0 t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc0 ht66 ? 40 ht66 ? 50 ht66 ? 60 t1acp0 t1bcp ? t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc1 ht66 ? 40 t ? cp1 t ? cp0 tmpc1 ht66 ? 50 ht66 ? 60 t ? cp1 t ? cp0 t ? cp1 t ? cp0 tm input/output pin control registers list
ht66f20 tm function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 104 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 105 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

ht66f30 tm function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 104 ?e???a?? 18? ?01? rev. 1.90 105 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

ht66f40 tm0 & tm2 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 106 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 107 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

ht66f40 tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 106 ?e???a?? 18? ?01? rev. 1.90 107 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

ht66f50 and ht66f60 tm0, tm2, tm3 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 108 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 109 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

ht66f50 and ht66f60 tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.90 108 ?e???a?? 18? ?01? rev. 1.90 109 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tmpc0 register ? ht66f20 bit 7 6 5 4 3 2 1 0 name t1cp1 t1cp0 t0cp0 r/w r/w r/w r/w por 0 1 1 bit 7~6 unimplemented, read as 0 bit 5 t1cp1 : tp1_1 pin control 0: disable 1: enable bit 4 t1cp0 : tp1_0 pin control 0: disable 1: enable bit 3~1 unimplemented, read as 0 bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable ? ht66f30 bit 7 6 5 4 3 2 1 0 name t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 1 0 1 0 1 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 unimplemented, read as 0 bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable
rev. 1.90 110 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 111 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name t1acp0 t1bcp ? t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 1 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 t1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable
rev. 1.90 110 ?e???a?? 18? ?01? rev. 1.90 111 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tmpc1 register ? ht66f40 bit 7 6 5 4 3 2 1 0 name t ? cp1 t ? cp0 r/w r/w r/w por 0 1 bit 7~2 unimplemented, read as 0 bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable ? ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name t ? cp1 t ? cp0 t ? cp1 t ? cp0 r/w r/w r/w r/w r/w por 0 1 0 1 bit 7~6 unimplemented, read as 0 bit 5 t3cp1 : tp3_1 pin control 0: disable 1: enable bit 4 t3cp0 : tp3_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable
rev. 1.90 11 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 11 ? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom programming considerations the tm counte r regi sters and the capt ure/compare ccraand ccrb regi sters, bei ng ei ther 10- bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer , reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. data bus 8-bit buffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm counter register (read only) tm ccra register (read/write) tm ccrb register (read/write) as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the "mov" ins truction to acces s the ccra and ccrb low byte regis ters, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. write data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is re ad di rectly fr om th e hig h by te re gisters an d sim ultaneously da ta is la tched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer.
rev. 1.90 11 ? ?e???a?? 18? ?01? rev. 1.90 11 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin ht66 ?? 0 10- ? it ctm 0 tck0 tp0_0 ht66 ?? 0 10- ? it ctm 0 tck0 tp0_0 ? tp0_1 ht66 ? 40 10- ? it ctm 0 tck0 tp0_0 ? tp0_1 ht66 ? 50 10- ? it ctm 0 ? ? tck0 ? tck ? tp0_0 ? tp0_1 ? tp ? _0 ? tp ? _1 ht66 ? 60 10- ? it ctm 0 ? ? tck0 ? tck ? tp0_0 ? tp0_1 ? tp ? _0 ? tp ? _1
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? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the applicat ion program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.90 114 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 115 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom compact type tm register description overall operati on of the compact tm is control led using six registe rs. a read only regist er pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmnc0 tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d ? d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d ? d ? d1 d0 tmnah d9 d8 compact tm register list (n=0 or 3) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh : tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmnah : tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8
rev. 1.90 114 ?e???a?? 18? ?01? rev. 1.90 115 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, whi le f and f tbc are other internal cl ocks, the de tails of whi ch ca n be found in the oscillator section. bit 3 tnon : tmn counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register , compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared wit h th e in ternal co unter's hi ghest th ree bi ts. th e re sult of th is comparison ca n be sel ected to cl ear the int ernal count er if the tnc clr bit is set to zero. setting the tnccl r bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all thre e bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value.
rev. 1.90 116 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 117 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare mat ch output mode, the tnio1 and tnio0 bit s det ermine how the tm output pin changes state when a compare match occurs from the compara tor a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modi fed by cha nging the se two bit s. it is nec essary to cha nge the val ues of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running.
rev. 1.90 116 ?e???a?? 18? ?01? rev. 1.90 117 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to sel ect the me thod whic h cl ears the count er. rem ember tha t the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.90 118 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 119 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or ti mer/counter mod e. th e op erating mo de is sel ected usi ng th e tn m1 an d tn m0 bits in the tmnc1 register . compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to "00" respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare ma tch oc curs fro m com parator p, th e ot her is whe n th e ccr p bi ts ar e al l ze ro whi ch allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches i ts maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated aft er a com pare ma tch occ urs from com parator a. the tnpf int errupt reque st fla g, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in whi ch th e tm ou tput pi n ch anges sta te ar e de termined by th e co ndition of th e tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from compa rator a. the ini tial condi tion of the tm output pin, whic h is set up aft er the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function.
rev. 1.90 118 ?e???a?? 18? ?01? rev. 1.90 119 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x? ?? ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin time ccrp =0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed ?? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 o?tp?t pin set to initial level low if tnoc =0 o?tp?t toggle with tna? flag note tnio [1:0 ] = 10 active high o?tp?t select he?e tnio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tna? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol is high compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.90 1 ? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x? ?? ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin time ccra =0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed ?? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1 ; tnm [1:0 ] = 00 o?tp?t pin set to initial level low if tnoc =0 o?tp?t toggle with tna? flag note tnio [1:0 ] = 10 active high o?tp?t select he?e tnio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tna? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol is high tnp? not gene?ated no tna? flag gene?ated on ccra ove?flow o?tp?t does not change compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.90 1?0 ?e???a?? 18? ?01? rev. 1.90 1 ? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. thepwmfunction within the tm is useful for applications which require functions such as motor control, heating co ntrol, il lumination co ntrol et c. by pr oviding a sig nal of fi xed fre quency bu t of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is ext remely fle xible. in the pwm mode , the tncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp regi sters are used to generat e the pwm waveform , one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 d ? t ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra d ? t ? 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pwm output period is determined by the ccraregister value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.90 1 ?? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin ( tnoc =1) time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? stop if tnon ?it low co?nte? reset when tnon ?et??ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm d?t? c?cle set ?? ccra pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set ?? ccrp tm o / p pin ( tnoc =0) pwm mode C tndpx=0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.90 1?? ?e???a?? 18? ?01? rev. 1.90 1 ?? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin ( tnoc =1) time co?nte? clea?ed ?? ccra pa?se res?me co?nte? stop if tnon ?it low co?nte? reset when tnon ?et??ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm d?t? c?cle set ?? ccrp pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set ?? ccra tm o / p pin ( tnoc =0) pwm mode C tndpx=1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.90 1 ? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive two external output pins. stm name tm no. tm input pin tm output pin ht66 ?? 0 10- ? it stm 1 tck1 tp1_0 ? tp1_1 ht66 ?? 0 ht66 ? 40 16- ? it stm ? tck ? tp ? _0 ? tp ? _1 ht66 ? 50 16- ? it stm ? tck ? tp ? _0 ? tp ? _1 ht66 ? 60 16- ? it stm ? tck ? tp ? _0 ? tp ? _1
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? ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? standard type tm block diagram standard tm operation there are two sizes of standard tms, one is 10-bits wide and the other is 16-bits wide. at the core is a 10 or 16-bi t c ount-up c ounter whi ch i s dri ven by a use r se lectable i nternal or e xternal c lock sourc e. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of ch anging th e va lue of th e 10 or 16- bit co unter usi ng th e ap plication pro gram, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.90 1?4 ?e???a?? 18? ?01? rev. 1.90 1 ? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d6 d5 d4 d ? d ? d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d ? d ? d1 d0 tm1ah d9 d8 10-bit standard tm register list (for ht66f20) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm ? c0 t ? pau t ? ck ? t ? ck1 t ? ck0 t ? on tm ? c1 t ? m1 t ? m0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr tm ? dl d7 d6 d5 d4 d ? d ? d1 d0 tm ? dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 tm ? al d7 d6 d5 d4 d ? d ? d1 d0 tm ? ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 tm ? rp d7 d6 d5 d4 d ? d ? d1 d0 16-bit standard tm register list (for ht66f40/ht66f50/ht66f60)
rev. 1.90 1 ? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 10-bit standard tm register list C ht66f20 ? tm1c0 register C 10-bit stm bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, whi le f and f tbc are other internal cl ocks, the de tails of whi ch ca n be found in the oscillator section. bit 3 t1on : tm1 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register , compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared wit h th e in ternal co unter's hi ghest th ree bi ts. th e re sult of th is comparison ca n be sel ected to cl ear the int ernal count er if the t1c clr bit is set to zero. setting the t1cclr bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all thre e bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value.
rev. 1.90 1?6 ?e???a?? 18? ?01? rev. 1.90 1 ? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1c1 register C 10-bit stm bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0 : select tm1 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1m1 and t1m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1 01: input capture at falling edge of tp1_0, tp1_1 10: input capture at falling/rising edge of tp1_0, tp1_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare mat ch output mode, the t1io1 and t1io0 bit s det ermine how the tm output pin changes state when a compare match occurs from the compara tor a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register. note that the output level requested by the t1io1 and t1io0 bits must be different from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modi fed by cha nging the se two bit s. it is nec essary to cha nge the val ues of the t1io1 and t1io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running.
rev. 1.90 1 ? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1oc : tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/co unter mode. in the compare mat ch outp ut mode it det ermines the log ic le vel of the tm out put pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1dpx : tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparatror p match 1: tm1 comparatror a match this bit is used to sel ect the me thod whic h cl ears the count er. rem ember tha t the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.90 1?8 ?e???a?? 18? ?01? rev. 1.90 1 ? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1dl register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 ? tm1dh register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 ? tm1al register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 ? tm1ahregister C 10-bit stm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8
rev. 1.90 1 ? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 16-bit standard tm register list - ht66f40/ht66f50/ht66f60 ? tm2c0 register C 16-bit stm bit 7 6 5 4 3 2 1 0 name t ? pau t ? ck ? t ? ck1 t ? ck0 t ? on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2, t2ck1, t2ck0 : select tm2 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: undefned 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, whi le f and f tbc are other internal cl ocks, the de tails of whi ch ca n be found in the oscillator section. bit 3 t2on : tm2 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.90 1?0 ?e???a?? 18? ?01? rev. 1.90 1 ? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm2c1 register C 16-bit stm bit 7 6 5 4 3 2 1 0 name t ? m1 t ? m0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2m1 and t2m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare mat ch output mode, the t2io1 and t2io0 bit s det ermine how the tm output pin changes state when a compare match occurs from the compara tor a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register. note that the output level requested by the t2io1 and t2io0 bits must be different from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modi fed by cha nging the se two bit s. it is nec essary to cha nge the val ues of the t2io1 and t2io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running.
rev. 1.90 1 ?? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/co unter mode. in the compare mat ch outp ut mode it det ermines the log ic le vel of the tm out put pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2dpx : tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bit is used to sel ect the me thod whic h cl ears the count er. rem ember tha t the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.90 1?? ?e???a?? 18? ?01? rev. 1.90 1 ?? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm2dl register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 16-bit counter bit 7~bit 0 ? tm2dh register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dh : tm2 counter high byte register bit 7~bit 0 tm2 16-bit counter bit 15~bit 8 ? tm2al register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 16-bit ccra bit 7~bit 0 ? tm2ah register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2ah : tm2 ccra high byte register bit 7~bit 0 tm2 16-bit ccra bit 15~bit 8 ? tm2rp register C 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2rp : tm2 ccrp register bit 7~bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15~bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256 (1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared wit h th e in ternal co unter's hi ghest ei ght bi ts. th e re sult of th is comparison ca n be sel ected to cl ear the int ernal count er if the t2c clr bit is set to zero. setting the t2cclr bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all ei ght bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value.
rev. 1.90 1 ? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register . compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare ma tch fro m com parator p, th e ot her is whe n th e cc rp bi ts ar e al l ze ro whi ch al lows the counter to overfow . here both tnaf and tnpf int errupt reque st fags for compa rator a and comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is hi gh no tn pf in terrupt re quest fag wil l be ge nerated. in th e co mpare mat ch out put mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in whi ch th e tm ou tput pi n ch anges sta te ar e de termined by th e co ndition of th e tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from compa rator a. the ini tial condi tion of the tm output pin, whic h is set up aft er the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.90 1?4 ?e???a?? 18? ?01? rev. 1.90 1 ? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ccra ccrp 0x ??? / 0x ???? co ? nte? ove ? flow ccra int. ? lag tna ? ccrp int. ? lag tnp ? ccrp > 0 co ? nte? clea ? ed ?? ccrp val ?e tm o/p pin tnon ? it pa ? se co ? nte? reset o ? tp? t pin set to initial level low if tnoc = 0 o ? tp? t tog g le with tna ? flag he ? e tnio1 ? tnio0 = 11 tog g le o ? tp? t select now tnio1 ? tnio0 = 10 active hig h o ? tp? t select o ? tp? t not affected ?? tna ? flag . remains hig h ? ntil ? eset ?? tnon ? it tncclr = 0; tnm[1:0] = 00 tn pau ? it res ? me stop time ccrp > 0 ccrp = 0 tnpol ? it o ? tp? t pin reset to initial val ?e o ? tp? t inve? ts when tnpol is hig h o ? tp? t cont ? olled ?? othe ? pin - sha ? ed f ? nction co ? nte? val ?e compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.90 1 ? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ccrp ccra 0x ??? / 0x ???? ccra = 0 co ? nte? ove ? flows ccrp int. ? lag tnp ? ccra int. ? lag tna ? ccra > 0 co ? nte? clea ? ed ?? ccra val ?e tm o/p pin tnon ? it pa ? se co ? nte? reset o ? tp? t pin reset to initial val ?e o ? tp? t pin set to initial level low if tnoc = 0 o ? tp? t tog g le with tna ? flag he ? e tnio1 ? tnio0 = 11 tog g le o ? tp? t select now tnio1 ? tnio0 = 10 active hig h o ? tp? t select tn pau ? it res ? me stop time tnp ? not g ene ? ated no tna ? flag g ene ? ated on ccra ove ? flow o ? tp? t does not chang e ccra = 0 o ? tp? t inve? ts when tnpol is hig h tnpol ? it tncclr = 1; tnm[1:0] = 00 o ? tp? t cont ? olled ?? othe ? pin - sha ? ed f ? nction o ? tp? t not affected ?? tna ? flag ? emains hig h ? ntil ? eset ?? tnon ? it co ? nte? val ?e compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
rev. 1.90 1?6 ?e???a?? 18? ?01? rev. 1.90 1 ? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 registe r should be set to 10 respect ively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is ext remely fle xible. in the pwm mode , the tnccl r bit has no ef fect as the pwm period. both of the ccraand ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 10-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 d ? t ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the stm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccraregister is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.90 1 ? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 1?9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 10-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra d ? t ? 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pwm output period is determined by the ccraregister value together with the tm clock while the pwm duty cycle is defned by the ccrp register value. 16-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 pe ? iod ccrp ? 56 655 ? 6 d ? t ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2256)=f sys /2048=7.8125khz, duty=128/(2256)=25%. if the duty value defned by the ccraregister is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 pe ? iod ccra d ? t ? ccrp ? 56 655 ? 6 the pwm output period is determined by the ccraregister value together with the tm clock while the pwm duty cycle is defned by the (ccrp x 256) except when the ccrp value is equal to 0.
rev. 1.90 1?8 ?e???a?? 18? ?01? rev. 1.90 1 ? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin ( tnoc =1) time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? stop if tnon ?it low co?nte? reset when tnon ?et??ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm d?t? c?cle set ?? ccra pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set ?? ccrp tm o / p pin ( tnoc =0) pwm mode C tndpx=0 note: 1. here tndpx=0, counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.90 140 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 141 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnpol ccrp int . ?lag tnp? ccra int . ?lag tna? tm o / p pin ( tnoc =1) time co?nte? clea?ed ?? ccra pa?se res?me co?nte? stop if tnon ?it low co?nte? reset when tnon ?et??ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm d?t? c?cle set ?? ccrp pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnpol = 1 pwm pe?iod set ?? ccra tm o / p pin ( tnoc =0) pwm mode C tndpx=1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.90 140 ?e???a?? 18? ?01? rev. 1.90 141 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 registe r should be set to 10 respect ively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.

? ? ? ? ? ?? ? ? ?? single pulse generation
rev. 1.90 14 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 14? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o/p pin (tnoc=0) tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 1 1 and can not be changed
rev. 1.90 14? ?e???a?? 18? ?01? rev. 1.90 14 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of ove rflow int errupt sig nals from the ccrp ca n be a useful me thod in me asuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode.
rev. 1.90 144 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 145 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ccrp co?nte? val?e co?nte? ove?flow ccrp int. ?lag tnp? ccra int. ?lag tna? tnon pa?se co?nte? reset tnpau res?me stop time yy xx ccra val?e xx tm capt??e pin tpn_x yy tnio [1:0] val?e 00 - rising edge 01 - ?alling edge 11 - disa?le capt??e active edge active edge xx 10 - both edges edge yy tnm [1:0] = 01 active capture input mode note: 1. tnm [1:0]=01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.90 144 ?e???a?? 18? ?01? rev. 1.90 145 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom enhanced type tm C etm the enhanced type tm contains fve operating modes, which are compare match output, timer/event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. etm name tm no. tm input pin tm output pin ht66 ?? 0 ht66 ?? 0 10- ? it etm 1 tck1 tp1a; tp1b_0 ? tp1b_1 ht66 ? 40 10- ? it etm 1 tck1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? ht66 ? 50 10- ? it etm 1 tck1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? ht66 ? 60 10- ? it etm 1 tck1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ?
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rev. 1.90 146 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 147 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the applicat ion program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr tm1c ? t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d ? d ? d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d ? d ? d1 d0 tm1ah d9 d8 tm1bl d7 d6 d5 d4 d ? d ? d1 d0 tm1bh d9 d8 10-bit enhanced tm register list (if etm is tm1)
rev. 1.90 146 ?e???a?? 18? ?01? rev. 1.90 147 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 10-bit enhanced tm register list C ht66f30/ht66f40/ht66f50/ht66f60 ? tm1c0 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, whi le f and f tbc are other internal cl ocks, the de tails of whi ch ca n be found in the oscillator section. bit 3 t1on : tm1 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register , compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared wit h th e in ternal co unter's hi ghest th ree bi ts. th e re sult of th is comparison ca n be sel ected to cl ear the int ernal count er if the t1c clr bit is set to zero. setting the t1cclr bit to zero ensures tha t a com pare ma tch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all thre e bit s to ze ro is in ef fect al lowing the count er to overfl ow at it s maximum value.
rev. 1.90 148 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 149 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1c1 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running.
rev. 1.90 148 ?e???a?? 18? ?01? rev. 1.90 149 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/co unter mode. in the compare mat ch outpu t mode it det ermines the log ic le vel of the tm out put pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm cont ains thre e com parators, compara tor a, comparat or b and comparator p, but only compa rator a or compa rator pan be sel ected to cl ear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the single puls e or input capture mode.
rev. 1.90 150 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 151 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1c2 register C 10-bit etm bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be swit ched of f be fore an y ch anges ar e ma de to th e t1 bm1 an d t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the compara tor b. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator b. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bit s must be dif ferent from the ini tial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bit s det ermine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running.
rev. 1.90 150 ?e???a?? 18? ?01? rev. 1.90 151 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down
rev. 1.90 15 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 15? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1dl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 ? tm1dh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 ? tm1al register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 ? tm1ah register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 ? tm1bl register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1bl : tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0
rev. 1.90 15? ?e???a?? 18? ?01? rev. 1.90 15 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? tm1bh register C 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1bh : tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9~bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register . etm operating mode ccra compare match output mode ccra timer/counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compa ? e match o ? tp ? t mode ccrb time ? /co ? nte ? mode ccrb pwm o ? tp ? t mode ccrb single p ? lse o ? tp ? t mode ccrb inp ? t capt ?? e mode shuplwwhgqrwshuplwwhg
rev. 1.90 154 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 155 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a c ounter overfow , a compare m atch from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow . here both the tnaf and tnpf interrupt request fags for comparator aand comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condi tion howeve r only cha nges sta te when an tnaf or tnbf int errupt request fag is generated after a compare match occurs from comparator aor comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place.
rev. 1.90 154 ?e???a?? 18? ?01? rev. 1.90 155 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x??? ccrp ccra tnon tnpau tnapol ccrp int. ?lag tnp? ccra int. ?lag tna? tpna o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed ?? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 00 o?tp?t pin set to initial level low if tnaoc =0 o?tp?t toggle with tna? flag note tnaio [1:0 ] = 10 active high o?tp?t select he?e tnaio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tna? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high etm ccra compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.90 156 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 157 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x??? ccrp ccrb tnon tnpau tnbpol ccrp int. ?lag tnp? ccrb int. ?lag tnb? tpnb o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed ?? ccrp val?e pa?se res?me stop co?nte? resta?t tncclr = 0; tnbm [1:0 ] = 00 o?tp?t pin set to initial level low if tnboc =0 o?tp?t toggle with tnb? flag note tnbio [1:0 ] = 10 active high o?tp?t select he?e tnbio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tnb? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high etm ccrb compare match output mode C tncclr=0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.90 156 ?e???a?? 18? ?01? rev. 1.90 157 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x??? ccrp ccra tnon tnpau tnapol ccrp int. ?lag tnp? ccra int. ?lag tna? tpna o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed ?? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1; tnam [1:0 ] = 00 o?tp?t pin set to initial level low if tnaoc =0 o?tp?t toggle with tna? flag note tnaio [1:0 ] = 10 active high o?tp?t select he?e tnaio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tna? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high tnp? not gene?ated no tna? flag gene?ated on ccra ove?flow o?tp?t does not change etm ccra compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.90 158 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 159 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e 0x??? ccrb ccra tnon tnpau tnbpol ccrb int. ?lag tnb? ccra int. ?lag tna? tpnb o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed ?? ccra val?e pa?se res?me stop co?nte? resta?t tncclr = 1; tnbm [1:0 ] = 00 o?tp?t pin set to initial level low if tnboc =0 o?tp?t toggle with tnb? flag note tnbio [1:0 ] = 10 active high o?tp?t select he?e tnbio [1:0 ] = 11 toggle o?tp?t select o?tp?t not affected ?? tnb? flag . remains high ?ntil ?eset ?? tnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high no tna? flag gene?ated on ccra ove?flow etm ccrb compare match output mode C tncclr=1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.90 158 ?e???a?? 18? ?01? rev. 1.90 159 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. with the tncclr bit set high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bit s are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccr a an d ccr b re gisters ca n be use d to set up di fferent dut y cy cle va lues to pro vide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the compara tor a, compara tor b or compara tor p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform.
rev. 1.90 160 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 161 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 a d ? t ? ccra b d ? t ? ccrb if f sys =16mhz, tm clock source select f sys /4, ccrp=100b, ccra=128 and ccrb=256, the tp1a pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. the tp1b_n pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=256/512=50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 ...... 511 512 ...... 1021 1022 1023 pe ? iod 1 ? ? ...... 511 51 ? ...... 10 ? 1 10 ?? 10 ?? b d ? t ? ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ? 56 51 ? 768 10 ? 4 1 ? 80 15 ? 6 179 ? ? 046 a d ? t ? (ccra ? ) ? 1 b d ? t ? (ccrb ? ) ? 1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 pe ? iod ? 4 6 10 ?? 10 ? 4 ? 04 ? ? 044 ? 046 b d ? t ? (ccrb ? ) ? 1
rev. 1.90 160 ?e???a?? 18? ?01? rev. 1.90 161 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnapol ccra int . ?lag tna? ccrb int . ?lag tnb? tpna pin ( tnaoc =1) time co?nte? clea?ed ?? ccrp pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 00 o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high ccrb ccrp int . ?lag tnp? tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set ?? ccra d?t? c?cle set ?? ccrb pwm pe?iod set ?? ccrp d?t? c?cle set ?? ccra d?t? c?cle set ?? ccra etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty
rev. 1.90 16 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 16? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccra tnon tnpau tnbpol ccrb int . ?lag tnb? time co?nte? clea?ed ?? ccra pa?se res?me stop co?nte? resta?t tncclr = 1; tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 00 o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnbpol is high ccrb ccrp int . ?lag tnp? tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set ?? ccrb pwm pe?iod set ?? ccra etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0]=00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin
rev. 1.90 16? ?e???a?? 18? ?01? rev. 1.90 16 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrp ccra tnon tnpau tnapol ccra int . ?lag tna? ccrb int . ?lag tnb? tpna pin ( tnaoc =1) time pa?se res?me stop co?nte? resta?t tncclr = 0; tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnpwm [1:0 ] = 11 o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction o?tp?t inve?ts when tnapol is high ccrb ccrp int . ?lag tnp? tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set ?? ccra d?t? c?cle set ?? ccrb pwm pe?iod set ?? ccrp etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0]=1 1 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0])=00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.90 164 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 165 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccra tnon tnpau tnbpol ccra int . ?lag tna? ccrb int . ?lag tnb? time pa?se res?me stop co?nte? resta?t tncclr = 1 ; tnbm [1:0 ] = 10; tnpwm [1:0 ] = 11 o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin - sha?ed f?nction ccrb tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) d?t? c?cle set ?? ccrb pwm pe?iod set ?? ccra o?tp?t inve?ts when tnbpol is high ccrp int . ?lag tnp? etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0]=1 1 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0]=00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.90 164 ?e???a?? 18? ?01? rev. 1.90 165 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom single pulse mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge is a compare ma tch fro m com parator b, whi ch ca n be im plemented usi ng th e ap plication program. howeve r in the sing le pulse mode , the tnon bit ca n al so be ma de to aut omatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to co ntrol th e pu lse wid th of tpn a. th e cc ra-ccrb va lue ca n be use d to co ntrol th e pulse width of tpnb. a com pare ma tch from comparat or a and comparat or b will al so gene rate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. s/w command settnon or tckn pin transition ccrb leading edge ccra trailing edge s/w command clr tnon or ccra compare match tpna output pin tpnb output pin pulse width = (ccra-ccrb) value pulse width = ccra value counter value ccrb ccra 0 time tnon = 1 ccrb compare match s/w command clr tnon or ccra compare match ccrb trailing edge ccra leading edge tnon bit 0 ? 1 tnon bit 1 ? 0 tnon bit 1 ? 0 single pulse generation
rev. 1.90 166 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 167 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e ccrb ccra tnon tnpau tnapol ccrb int. ?lag tnb? ccra int. ?lag tna? tpna pin ( tnaoc =1) time co?nte? stopped ?? ccra pa?se res?me co?nte? stops ?? softwa?e co?nte? reset when tnon ?et??ns high tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnaio [1:0 ] = 11 ? tnbio [1:0 ] = 11 p?lse width set ?? ( ccra -ccrb ) o?tp?t inve?ts when tnbpol =1 tckn pin softwa?e t?igge? clea?ed ?? ccra match tckn pin t?igge? a?to. set ?? tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnbpol tpna pin ( tnaoc =0) tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) p?lse width set ?? ccra o?tp?t inve?ts when tnapol =1 etm C single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 1 1 and can not be changed
rev. 1.90 166 ?e???a?? 18? ?01? rev. 1.90 167 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active ed ge ca n be ei ther a ri sing ed ge, a fa lling ed ge or bo th ri sing an d fa lling ed ges; th e active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can sel ect the act ive tri gger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode.
rev. 1.90 168 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 169 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom co?nte? val?e yy ccrp tnon tnpau ccrp int. ?lag tnp? ccra int. ?lag tna? ccra val?e time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? reset tnam [1:0 ] = 01 tm capt??e pin tpna xx co?nte? stop tnaio [1:0] val?e xx yy xx yy active edge active edge active edge 00 ? rising edge 01 ? ?alling edge 10 ? both edges 11 ? disa?le capt??e etm ccra capture input mode note: 1. tnam [1:0]=01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.90 168 ?e???a?? 18? ?01? rev. 1.90 169 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ccrp co?nte? ove?flow ccrp int. ?lag tnp? ccrb int. ?lag tnb? tnon ?it pa ?se co ?n te? re set tnpau ?it res? me sto p yy xx ccrb val?e xx tm capt??e pin yy tnbio1? tnbio0 val?e 00 - rising edge 01 - ?alling edge 11 - disa?le capt??e active edge ac ti ve edge xx 10 - both edges active edges yy tnbm1? tnbm0 = 01 tim e co?nte? val?e etm ccrb capture input mode note: 1. tnbm [1:0]=01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.90 170 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 171 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom aanlog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins ht66 ?? 0 ht66 ?? 0 ht66 ? 40 ht66 ? 50 8 acs4 ? acs ? ~acs0 an0~an7 ht66 ? 60 1 ? acs4 ? acs ? ~acs0 an0~an11 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers.

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??? ? ? - ? - ? ? ? ? ? ? a/d converter structure a/d converter register description overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the adc data 12-bit value. the remaining three or four registers are control registers which setup the operating and control function of the a/d converter . register name bit 7 6 5 4 3 2 1 0 adrl(adr ? s=0) d ? d ? d1 d0 adrl(adr ? s=1) d7 d6 d5 d4 d ? d ? d1 d0 adrh(adr ? s=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adr ? s=1) d11 d10 d9 d8 adcr0 start eocb ado ?? adr ? s acs ? acs1 acs0 adcr1 acs4 v1 ? 5en vre ? s adck ? adck1 adck0 acerl ace7 ace6 ace5 ace4 ace ? ace ? ace1 ace0 ht66f20/ht66f30/ht66f40/ht66f50 a/d converter register list
rev. 1.90 170 ?e???a?? 18? ?01? rev. 1.90 171 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom register name bit 7 6 5 4 3 2 1 0 adrl(adr ? s=0) d ? d ? d1 d0 adrl(adr ? s=1) d7 d6 d5 d4 d ? d ? d1 d0 adrh(adr ? s=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adr ? s=1) d11 d10 d9 d8 adcr0 start eocb ado ?? adr ? s acs ? acs ? acs1 acs0 adcr1 acs4 v1 ? 5en vre ? s adck ? adck1 adck0 acerl ace7 ace6 ace5 ace4 ace ? ace ? ace1 ace0 acerh ace11 ace10 ace9 ace8 ht66f60 a/d converter register list a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted val ue. the se are a high byte regi ster, known as adrh, and a low byt e regi ster, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl, acerh to control the function and operation of the a/d converter, three or four control registers known as adcr0, adcr1, acerl and acerh are provided. these 8-bit registers defne functions such as the selection of whic h ana log cha nnel is con nected to the int ernal a/d con verter, the digi tised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register defne the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 or 12 analog inputs must be routed to the converter. it is the function of the acs4~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter . the acerh and acerl control registers contain the acer11~acer0 bits which determine which pins on port a, pe6, pe7, pf0 and pf1 are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input funct ion, cl earing the bit to ze ro wil l sel ect ei ther the i/o or othe r pin-sha red function. when th e pi n is sel ected to be an a/d in put, it s or iginal fu nction whe ther it is an i/ o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.90 17 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 17? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom adcr0 register ? ht66f20/ht66f30/ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name start eocb ado ?? adr ? s acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d c onversion process. the bit is norm ally l ow but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/of f control bit 0: adc module power on 1: adc module power of f this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as 0 bit 2~0 acs2, acs1, acs0 : select a/d channel (when acs4 is "0") 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter .
rev. 1.90 17? ?e???a?? 18? ?01? rev. 1.90 17 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom adcr0 register ? ht66f60 bit 7 6 5 4 3 2 1 0 name start eocb ado ?? adr ? s acs ? acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/d c onversion process. the bit is norm ally l ow but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/of f control bit 0: adc module power on 1: adc module power of f this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3, acs2, acs1, acs0 : select a/d channel (when acs4 is "0") 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 1010: an10 1011: an11 1100~1111:undefned, can't be used these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter .
rev. 1.90 174 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 175 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 v1 ? 5en vre ? s adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : selecte internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/l vd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as 0 bit 2~0 adck2, adck1, adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter .
rev. 1.90 174 ?e???a?? 18? ?01? rev. 1.90 175 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace5 ace4 ace ? ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 acerh register ? ht66f60 bit 7 6 5 4 3 2 1 0 name ace11 ace10 ace9 ace8 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 bit 3 ace11 : defne pf1 is a/d input or not 0: not a/d input 1: a/d input, an11 bit 2 ace10 : defne pf0 is a/d input or not 0: not a/d input 1: a/d input, an10 bit 1 ace9 : defne pe7 is a/d input or not 0: not a/d input 1: a/d input, an9 bit 0 ace8 : defne pe6 is a/d input or not 0: not a/d input 1: a/d input, an8
rev. 1.90 176 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 177 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom a/d operation the start bit in the adcr0 regi ster is used to sta rt and rese t the a/d co nverter. whe n the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the star t bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter . the eocb bit in the adcr0 regist er is used to indi cate when the analog to digit al conversion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register . although the a/d c lock sourc e i s det ermined by t he syst em c lock f sys , and by bits adck2~adck0, there are some li mitations on th e ma ximum a/d cl ock sou rce spe ed th at ca n be sel ected. as th e minimum value of permissible a/d clock period, t adck , is 0.5s, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000. doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s 32s 64s undefned ? mhz 500ns 1s 2s 4s 8s 16s 32s undefned 4mhz ? 50ns* 500ns 1s 2s 4s 8s 16s undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s 2s 4s 8s undefned 1 ? mhz 8 ? ns* 167ns* ??? ns* 667ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling the power on/of f funct ion of the a/d conve rter ci rcuitry is im plemented using the adoff bit in the adcr0 regi ster. thi s bit must be zero to power on the a/d conve rter. whe n the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the ti ming dia gram, must be al lowed befo re an a/d con version is ini tiated. eve n if no pins are sel ected for use as a/d input s by cl earing the ace1 1~ace0 bit s in the acerh and acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically.
rev. 1.90 176 ?e???a?? 18? ?01? rev. 1.90 177 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a, pe6, pf7, pf0 or pf1 as well as other functions. the ace11~ace0 bits in the acerh and acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace11~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program co ntrol to ch ange th eir fu nction be tween a/d in puts an d ot her fu nctions. all pu ll- high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac, pec or pfc port control register to enable the a/d input as when the ace11~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
? ? ? ?? ? ? a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register . ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace11~ace0 bits in the acerh and acerl registers. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, eadi, must both be set high to do this.
rev. 1.90 178 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 179 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? step 6 the analog to digital conversion process can now be initialised by setting the star t bit in the adcr register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is compl ete when this bit goes low . when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur . note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, du ring whi ch ti me the pr ogram ca n co ntinue wit h ot her fu nctions. the ti me ta ken fo r the a/d conversion is 16t adck where t adck is equal to the a/d clock period.

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? ? ? - ? ? ? ? ?? - a/d conversion timing
rev. 1.90 178 ?e???a?? 18? ?01? rev. 1.90 179 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom programming considerations during microcontroller opera tions where the a/d conve rter is not bei ng used, the a/d int ernal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. wh en thi s ha ppens, th e in ternal a/d co nverter ci rcuits wil l no t co nsume po wer irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value(v dd or v ref )4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converte r. except for the digit ised zero value , the subsequent digit ised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

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? ideal a/d transfer function
rev. 1.90 180 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 181 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst ex ample, th e me thod of pol ling th e eoc b bi t in th e adcr0 re gister is use d to de tect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; se lect f sys /8 as a/d cl ock an d sw itch of f 1. 25v clr adoff mov a,0fh ; se tup ac erl and ac erh to co nfgure pi ns an 0~an3 mov acerl,a mov a,00h mov acerh,00h ; ace rh is on ly f or ht 66f60 mov a,00h mov adcr0,a ; en able and co nnect an 0 ch annel to a/ d co nverter : start_conversion: clr start ; hi gh pu lse on st art bit to in itiate co nversion set start ; re set a/ d clr start ; star t a/ d polling_eoc: sz eocb ; pol l th e ad cr0 re gister eo cb bit to de tect en d of a/ d co nversion jmp polling_eoc ; co ntinue po lling mov a,adrl ; read lo w by te co nversion res ult va lue mov adrl_buffer,a ; sa ve re sult to use r de fned re gister mov a,adrh ; read hi gh by te co nversion res ult va lue mov adrh_buffer,a ; sa ve re sult to use r de fned re gister : : jmp start_conversion ; sta rt ne xt a/d co nversion
rev. 1.90 180 ?e???a?? 18? ?01? rev. 1.90 181 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; se lect f sys/ 8 as a/d cl ock an d sw itch of f 1. 25v clr adoff mov a,0fh ; se tup ac erl and ac erh to co nfgure pi ns an 0~an3 mov acerl,a mov a,00h mov acerh,00h ; ace rh is on ly f or ht 66f60 mov a,00h mov adcr0,a ; en able and co nnect an 0 ch annel to a/ d co nverter start_conversion: clr start ; hi gh pu lse on sta rt bit to in itiate co nversion set start ; re set a/ d clr start ; star t a/ d clr adf ; cl ear ad c in terrupt req uest fag set ade ; enable adc interrupt set emi ; ena ble glo bal int errupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; sa ve ac c to us er de fned me mory mov a,status mov status_stack,a ; sa ve sta tus to use r de fned me mory : : mov a,adrl ; read lo w by te co nversion res ult va lue mov adrl_buffer,a ; sa ve re sult to use r de fned re gister mov a,adrh ; read hi gh by te co nversion res ult va lue mov adrh_buffer,a ; sa ve re sult to use r de fned re gister : : exit_int_isr: mov a,status_stack mov status,a ; r estore stat us fr om us er def ned me mory mov a,acc_stack ; re store ac c fro m us er de fned me mory reti
rev. 1.90 18 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 18? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom comparators two independent analog comparators are contained within these devices. these functions offer fexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator comparator operation the device con tains two com parator func tions whic h are used to com pare two ana log vol tages and provide an output based on their difference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a sha red i/o pi n. addi tional co mparator func tions in clude, out put pol arity, hyst eresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spu rious ou tput sig nals ma y be ge nerated on th e co mparator ou tput du e to th e slo w rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the posit ive and nega tive input s signa ls are at the sam e volt age level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value.
rev. 1.90 18? ?e???a?? 18? ?01? rev. 1.90 18 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom comparator registers there are two registers for overall comparator operation, one for each comparator. as corresponding bits in the two registers have identical functions, they following register table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0sel c0en c0pol c0out c0os c0hyen cp1c c1sel c1en c1pol c1out c1os c1hyen comparator registers list cp0c registe bit 7 6 5 4 3 2 1 0 name c0sel c0en c0pol c0out c0os c0hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c0sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c0en : comparator on/off control 0: off 1: on this is the compa rator on/of f cont rol bit . if the bit is ze ro the com parator wil l be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c0pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c0out bit will be inverted. bit 4 c0out : comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit.
rev. 1.90 184 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 185 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 c0os : output path select 0: c0x pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0 and the c0sel bit is 1 the comparator output is connected to an external c0x pin. if the bit is set to 1 or the c0sel bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 c0hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. cp1c register bit 7 6 5 4 3 2 1 0 name c1sel c1en c1pol c1out c1os c1hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c1sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c1en : comparator on/off control 0: off 1: on this is the compa rator on/of f cont rol bit . if the bit is ze ro the com parator wil l be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c1pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c1out bit will be inverted. bit 4 c1out : comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit.
rev. 1.90 184 ?e???a?? 18? ?01? rev. 1.90 185 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 3 c1os : output path select 0: c1x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c1sel bit is "1" the comparator output is connected to an external c1x pin. if the bit is set to "1" or the c1sel bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 c1hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. comparator interrupt each also possesses it s own int errupt functi on. whe n any one of the cha nges stat e, it s rel evant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control re gister is "1") or read as port data re gister value (port control re gister is "0") if the comparator function is enabled.
rev. 1.90 186 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 187 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom serial interface module C sim these devices co ntain a ser ial in terface mod ule, whi ch inc ludes bo th the fo ur li ne spi int erface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the sp i interface specif cation can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a fu ll du plex syn chronous ser ial da ta li nk. it is a fo ur li ne in terface wit h pi n names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with no rmal i/ o pi ns an d wit h the i 2 c function pins, th e spi int erface mu st frst be en abled by selecting the sim enable confguration option and setting the correct bits in the simc0 and simc2 registers. after the spi confguration option has been confgured it can also be additionally disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is ca rried out in a sla ve/master mode wit h al l dat a tra nsfer ini tiations bei ng implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol and csen bit enabled or disable select
rev. 1.90 186 ?e???a?? 18? ?01? rev. 1.90 187 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several configuration options ass ociated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. another two spi confguration options determine if the csen and wcol bits are to be used. spi master/slave connection

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? ? ? ? ? spi bolck diagram
rev. 1.90 188 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 189 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d ? d ? d1 d0 simc ? d7 d6 ckpolb ckeg mls csen wcol tr ? sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x: ? nknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the dat a tra nsmission cl ock freque ncy. alt hough not conne cted wit h the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.90 188 ?e???a?? 18? ?01? rev. 1.90 189 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0
rev. 1.90 190 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 191 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol tr ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck li ne wil l be low when the cl ock is ina ctive. whe n the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed othe rwise an errone ous cl ock edge ma y be gene rated. the ckpolb bit determines the base condi tion of the cl ock li ne, if the bit is high, the n the sck li ne will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via confguration option. bit 0 trf : spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete fag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt.
rev. 1.90 190 ?e???a?? 18? ?01? rev. 1.90 191 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom spi communication after the spi int erface is ena bled by set ting the simen bit high, then in the mast er mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is com plete, the trf fla g wil l be set aut omatically, but must be cl eared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0
rev. 1.90 19 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 19? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

? ???? ? ? ?? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ?? ? ?? ?? ?? ? ? ?? ?? ???? ?? ? ?? ? ? ? ?? spi slave mode timing C ckeg=1

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? ? ? ? ? ? - ? ?? ? ? ?? ? ? ?? ?? ? ?? ? ??????? ?? ? ?? ?? ? spi transfer control flowchart
rev. 1.90 19? ?e???a?? 18? ?01? rev. 1.90 19 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom me mory et c. ori ginally de veloped by phi lips, it is a two li ne lo w spe ed ser ial in terface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the sla ve devi ce. both ma ster and sla ve ca n tra nsmit and rec eive dat a, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a configuration op tion de termines th e de bounce ti me of th e i 2 c interface. th is use s th e system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. to achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no de ? o ? nce f sys > ? mhz f sys > 5mhz ? s ? stem clock de ? o ? nce f sys > 4mhz f sys > 10mhz 4 s ? stem clock de ? o ? nce f sys > 8mhz f sys > ? 0mhz i 2 c minimum f sys frequency
rev. 1.90 194 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 195 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom
i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note t hat t he sima re gister a lso ha s t he na me simc2 whi ch i s use d by t he spi func tion. bi t sime n and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simc1 hc ? haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d ? d ? d1 d0 sima iica6 iica5 iica4 iica ? iica ? iica1 iica0 d0 i 2 c registers list
rev. 1.90 194 ?e???a?? 18? ?01? rev. 1.90 195 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0
rev. 1.90 196 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 197 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom simc1 register bit 7 6 5 4 3 2 1 0 name hc ? haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the haas fag is the addre ss ma tch fag. thi s fag is used to det ermine if the sla ve device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. this fag will be 1 when the i 2 c bus is busy which will occur when a star t signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is th e i 2 c slave read/write fl ag. th is fl ag de termines whe ther the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable - must be cleared by the application program after wake-up this bit should be set to 1 to enable the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation.
rev. 1.90 196 ?e???a?? 18? ?01? rev. 1.90 197 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the rxak fag is the receiver acknowledge fag. when the rxak fag is 0, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por ? nknown sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica ? iica ? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por ? nknown bit 7~1 iica6~iica0 : i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6~bit 0. the sima re gister is al so use d by th e spi in terface bu t ha s th e na me simc 2. th e sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program.
rev. 1.90 198 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 199 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

? ? ? ? ? ?-? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a star t signal, a slave device address transmission, a data transmission and finally a stop signal. when a star t signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initial ise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.
rev. 1.90 198 ?e???a?? 18? ?01? rev. 1.90 199 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom

? ? ? ? ? ? - ?? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this star t signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. as tart condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a star t sig nal by th e ma ster wil l be de tected by al l de vices on th e i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the star t signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be exa mined to see whet her the int errupt source has com e from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the sim d register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.90 ? 00 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?01 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address , any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its sla ve ad dress. th e or der of ser ial bi t tr ansmission is th e msb frst an d th e lsb la st. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver , the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sdaline and await the receipt of a stop signal from the master .
rev. 1.90 ?00 ?e???a?? 18? ?01? rev. 1.90 ? 01 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom
? ? ? ? ? ? ? ? - ?
- ? ? note: *when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
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i 2 c bus isr fow chart
rev. 1.90 ? 0 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?0? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it . the requi red divi sion rat io of the syste m cl ock is sel ected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. bit 0 unimplemented, read as 0
rev. 1.90 ?0? ?e???a?? 18? ?01? rev. 1.90 ? 0 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom interrupts interrupts are an important part of any microcontroller sys tem. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int3 and pint pins, while the internal interrupts are generated by various internal functions such as the tms, comparators, time base, l vd, eeprom, sim and the a/d converter . interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~int c3 regi sters whic h set up the prim ary int errupts, the sec ond is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disabl e individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes glo ? al emi compa ? ato ? cpne cpn ? n=0 o ? 1 intn pin intne intn ? n=0~ ? a/d conve ? te ? ade ad ? m ? lti-f ? nction m ? ne m ? n ? n=0~5 time base tbne tbn ? n=0 o ? 1 sim sime sim ? lvd lve lv ? eeprom dee de ? pint pin xpe xp ? tm tnpe tnp ? n=0~ ? tnae tna ? tnbe tnb ? interrupt register bit naming conventions
rev. 1.90 ? 04 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?05 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom interrupt register contents ? ht66f20 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0 ? int1 ? int0 ? cp0e int1e int0e emi intc1 ad ? m ? 1 ? m ? 0 ? cp1 ? ade m ? 1e m ? 0e cp1e intc ? m ??? tb1 ? tb0 ? m ??? m ?? e tb1e tb0e m ?? e m ? i0 t0a ? t0p ? t0ae t0pe m ? i1 t1a ? t1p ? t1ae t1pe m ? i ? de ? lv ? xp ? sim ? dee lve xpe sime ? ht66f30 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0 ? int1 ? int0 ? cp0e int1e int0e emi intc1 ad ? m ? 1 ? m ? 0 ? cp1 ? ade m ? 1e m ? 0e cp1e intc ? m ??? tb1 ? tb0 ? m ??? m ?? e tb1e tb0e m ?? e m ? i0 t0a ? t0p ? t0ae t0pe m ? i1 t1b ? t1a ? t1p ? t1be t1ae t1pe m ? i ? de ? lv ? xp ? sim ? dee lve xpe sime ? ht66f40 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0 ? int1 ? int0 ? cp0e int1e int0e emi intc1 ad ? m ? 1 ? m ? 0 ? cp1 ? ade m ? 1e m ? 0e cp1e intc ? m ??? tb1 ? tb0 ? m ??? m ?? e tb1e tb0e m ?? e m ? i0 t ? a ? t ? p ? t0a ? t0p ? t ? ae t ? pe t0ae t0pe m ? i1 t1b ? t1a ? t1p ? t1be t1ae t1pe m ? i ? de ? lv ? xp ? sim ? dee lve xpe sime
rev. 1.90 ?04 ?e???a?? 18? ?01? rev. 1.90 ? 05 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f50 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0 ? int1 ? int0 ? cp0e int1e int0e emi intc1 ad ? m ? 1 ? m ? 0 ? cp1 ? ade m ? 1e m ? 0e cp1e intc ? m ??? tb1 ? tb0 ? m ??? m ?? e tb1e tb0e m ?? e m ? i0 t ? a ? t ? p ? t0a ? t0p ? t ? ae t ? pe t0ae t0pe m ? i1 t1b ? t1a ? t1p ? t1be t1ae t1pe m ? i ? de ? lv ? xp ? sim ? dee lve xpe sime m ? i ? t ? a ? t ? p ? t ? ae t ? pe ? ht66f60 name bit 7 6 5 4 3 2 1 0 integ int ? s1 int ? s0 int ? s1 int ? s0 int1s1 int1s0 int0s1 int0s0 intc0 int ?? int1 ? int0 ? int ? e int1e int0e emi intc1 m ? 0 ? cp1 ? cp0 ? int ?? m ? 0e cp1e cp0e int ? e intc ? ad ? m ??? m ??? m ? 1 ? ade m ?? e m ?? e m ? 1e intc ? m ? 5 ? tb1 ? tb0 ? m ? 4 ? m ? 5e tb1e tb0e m ? 4e m ? i0 t ? a ? t ? p ? t0a ? t0p ? t ? ae t ? pe t0ae t0pe m ? i1 t1b ? t1a ? t1p ? t1be t1ae t1pe m ? i ? de ? lv ? xp ? sim ? dee lve xpe sime m ? i ? t ? a ? t ? p ? t ? ae t ? pe
rev. 1.90 ? 06 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?07 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom integ register ? ht66f20/ht66f30/ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ? ht66f60 bit 7 6 5 4 3 2 1 0 name int ? s1 int ? s0 int ? s1 int ? s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1, int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit5~4 int2s1, int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
rev. 1.90 ?06 ?e???a?? 18? ?01? rev. 1.90 ? 07 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom intc0 register ? ht66f20/ht66f30/ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name cp0 ? int1 ? int0 ? cp0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 cp0f : comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.90 ? 08 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?09 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f60 bit 7 6 5 4 3 2 1 0 name int ?? int1 ? int0 ? int ? e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 int2f : int2 interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 int2e : int2 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.90 ?08 ?e???a?? 18? ?01? rev. 1.90 ? 09 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom intc1 register ? ht66f20/ht66f30/ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name ad ? m ? 1 ? m ? 0 ? cp1 ? ade m ? 1e m ? 0e cp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 cp1f : comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e : comparator 1 interrupt control 0: disable 1: enable
rev. 1.90 ? 10 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ? 11 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f60 bit 7 6 5 4 3 2 1 0 name m ? 0 ? cp1 ? cp0 ? int ?? m ? 0e cp1e cp0e int ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 6 cp1f : comparator 1 interrupt request flag 0: no request 1: interrupt request bit 5 cp0f : comparator 0 interrupt request flag 0: no request 1: interrupt request bit 4 int3f : int3 interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 2 cp1e : comparator 1 interrupt control 0: disable 1: enable bit 1 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 0 int3e : int3 interrupt control 0: disable 1: enable
rev. 1.90 ?10 ?e???a?? 18? ?01? rev. 1.90 ? 11 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom intc2 register ? ht66f20/ht66f30/ht66f40/ht66f50 bit 7 6 5 4 3 2 1 0 name m ??? tb1 ? tb0 ? m ??? m ?? e tb1e tb0e m ?? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable
rev. 1.90 ? 1 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?1? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f60 bit 7 6 5 4 3 2 1 0 name ad ? m ??? m ??? m ? 1 ? ade m ?? e m ?? e m ? 1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 mf1e : multi-function interrupt 1 control 0: disable 1: enable
rev. 1.90 ?1? ?e???a?? 18? ?01? rev. 1.90 ? 1 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom intc3 register ? ht66f60 bit 7 6 5 4 3 2 1 0 name m ? 5 ? tb1 ? tb0 ? m ? 4 ? m ? 5e tb1e tb0e m ? 4e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf5f : multi-function interrupt 5 request fag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request fag 0: no request 1: interrupt request bit 4 mf4f : multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 3 mf5e : multi-function interrupt 5 control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf4e : multi-function interrupt 4 control 0: disable 1: enable
rev. 1.90 ? 14 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?15 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mfi0 register ? ht66f20/ht66f30 bit 7 6 5 4 3 2 1 0 name t0a ? t0p ? t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ? ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name t ? a ? t ? p ? t0a ? t0p ? t ? ae t ? pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.90 ?14 ?e???a?? 18? ?01? rev. 1.90 ? 15 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mfi1 register ? ht66f20 bit 7 6 5 4 3 2 1 0 name t1a ? t1p ? t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable ? ht66f30/ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name t1b ? t1a ? t1p ? t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1bf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.90 ? 16 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?17 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mfi2 register bit 7 6 5 4 3 2 1 0 name de ? lv ? xp ? sim ? dee lve xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf : sim interrupt request fag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 lve : lvd interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable mfi3 register ? ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name t ? a ? t ? p ? t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 0 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable
rev. 1.90 ?16 ?e???a?? 18? ?01? rev. 1.90 ? 17 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a or comparator b match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether th e re quest fag ac tually ge nerates a pro gram ju mp to th e re levant in terrupt ve ctor is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if othe r int errupt reque sts occ ur during thi s int erval, al though the int errupt wil l not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of th e in terrupt re quest fags whe n set wil l wak e-up the de vice if it is in sle ep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.90 ? 18 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?19 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 04h 08h 0ch 10h 14h 18h 1ch ?0h ?4h ?8h vector low p ? io ? it ? high req ? est ? lags ena ? le bits maste ? ena ? le req ? est ? lags ena ? le bits emi a ? to disa? led in isr inte ??? pts contained within m? lti - ?? nction inte ??? pts inte ??? pt name inte ??? pt name ht66 ?? 0 onl ? m ??? m. ?? nct . ? m ??e xp ? pint pin xpe emi ? ch lv ? lvd lve de ? eeprom dee emi emi emi emi emi emi emi emi emi sim ? sim sime t1b ? tm1 b t1be t1a ? tm1 a t1ae t1p ? tm1 p t1pe t0a ? tm0 a t0ae t0p ? tm0 p t0pe int0 ? int0 pin int0e int1 ? int1 pin int1e cp0 ? comp. 0 cp0e cp1 ? comp. 1 cp1e m? 0? m. ?? nct . 0 m? 0e m? 1? m. ?? nct . 1 m? 1e ad ? a/d ade emi m ??? m. ?? nct . ? m ??e tb0 ? time base 0 tb0e tb1 ? time base 1 tb1e xx? legend req ? est ? lag C no a ?t o ? eset in isr xx? req ? est ? lag C a? to ? es et in isr xxe ena ? le bit interrupt structure C ht66f20/ht66f30
rev. 1.90 ?18 ?e???a?? 18? ?01? rev. 1.90 ? 19 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 04h 0ch 14h 18h 1ch ?0h ?4h ?8h req ? est ? lags ena ? le bits inte ??? pts contained within m? lti - ?? nction inte ??? pts inte ??? pt name m ??? m. ?? nct . ? m ??e xp ? pint pin xpe emi lv ? lvd lve de ? eeprom dee emi emi emi emi emi emi emi emi emi sim ? sim sime t1b ? tm1 b t1be t1a ? tm1 a t1ae t1p ? tm1 p t1pe tp0a ? tm0 a t0ae tp0a ? tm0 p t0pe int0 ? int0 pin int0e int1 ? int1 pin int1e cp0 ? comp. 0 cp0e cp1 ? comp. 1 cp1e m? 0? m. ?? nct . 0 m? 0e m? 1? m. ?? nct . 1 m? 1e ad ? a/d ade emi m ??? m. ?? nct . ? m ??e tb0 ? time base 0 tb0e tb1 ? time base 1 tb1e t ? a? tm ? a t ? ae t ? p? tm ? p t ? pe t ? a? tm ? a t ? ae t ? p? tm ? p t ? pe ht66 ? 50 onl ? low p ? io ? it ? high xx? legend req ? est ? lag C no a ? to ? eset in isr xx? req ? est ? lag C a? to ? eset in isr xxe ena ? le bit vector req ? est ? lags ena ? le bits mas t e? ena ? le emi a ? to disa? led in isr inte ??? pt name 08h ? ch 10h interrupt structure C ht66f40/ht66f50
rev. 1.90 ?? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 04h 08h 14h 18h 1ch 20h 2ch 24h 34h 38h request flags enable bits emi auto disabled in isr interrupts contained within multi-function interrupts interrupt name xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit mf3f m. funct. 3 mf3e xpf pint pin xpe emi 28h lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e adf a/d ade emi mf2f m. funct. 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e t3af tm3 a t3ae t3pf tm3 p t3pe emi emi int2f int2 pin int2e int3f int3 pin int3e 0ch 10h mf5f m. funct. 5 mf5e emi 3ch 30h emi mf4f m. funct. 4 mf4e t2af tm2 a t2ae t2pf tm2 p t2pe low priority high vector request flags enable bits master enable interrupt name interrupt structure C ht66f60
rev. 1.90 ??0 ?e???a?? 18? ?01? rev. 1.90 ?? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int3. an external interrupt request will take place when the external interrupt request fags, int0f~int3f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int3e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int3f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator in terrupt is co ntrolled by th e two in ternal co mparators. a co mparator in terrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, wil l be aut omatically rese t and the emi bit wil l be aut omatically cl eared to disa ble other interrupts. multi-function interrupt within these devices there are up to six multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim interrupt, external peripheral interrupt, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf5f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that , alt hough the mult i-function interrupt fags wil l be aut omatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, sim interrupt, external peripheral interrupt, lvd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program.
rev. 1.90 ??? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective i nterrupt v ector a ddress, t he g lobal i nterrupt e nable b it, e mi, and a/d i nterrupt e nable b it, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupt the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section.
rev. 1.90 ??? ?e???a?? 18? ?01? rev. 1.90 ??? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select time base 1 time-out period 00: 4096/ f tb 01: 8192/ f tb 10: 16384/ f tb 11: 32768/ f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 256/ f tb 001: 512/ f tb 010: 1024/ f tb 011: 2048/ f tb 100: 4096/ f tb 101: 8192/ f tb 110: 16384/ f tb 111: 32768/ f tb

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?
?
time base interrupt
rev. 1.90 ?? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automa tically clea red to disable other int errupts, however only the multi -function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt ena ble bit , emi , ext ernal peri pheral int errupt ena ble bit , xpe, and assoc iated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a negat ive transi tion appears on the exte rnal periphera l interrupt pin, a subroutine cal l to the respective mul ti-function inte rrupt, wil l ta ke pla ce. whe n the ext ernal peri pheral inte rrupt is serviced, the emi bit wil l be aut omatically cl eared to disa ble oth er int errupts, howe ver onl y the multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin. eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eepro m interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom wr ite o r r ead cy cle e nds. to a llow th e p rogram t o bra nch t o it s resp ective i nterrupt v ector address, the gl obal in terrupt en able bi t, emi , ee prom int errupt en able bi t, dee , an d asso ciated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write or read cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be a lso a utomatically c leared. as t he de f fa g wi ll not be a utomatically c leared, i t ha s t o be cleared by the application program.
rev. 1.90 ??4 ?e???a?? 18? ?01? rev. 1.90 ?? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom lvd interrupt the low voltage det ector int errupt is co ntained wit hin th e mul ti-function int errupt. an lvd interrupt request will take place when the lvd interrupt request flag, lv f, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automa tically clea red to disable other int errupts, however only the multi -function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two interrupts each, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and sta ndard type tms the re are two int errupt reque st fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.90 ?? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom interrupt wake-up function each of the interrupt functions has the capa bility of waking up the microc ontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on th e ex ternal in terrupt pi ns, a lo w po wer sup ply vo ltage or co mparator in put ch ange may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling th e rel evant int errupt ena ble bit s, a reque sted int errupt ca n be preve nted from bei ng serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags , mf 0f~mf5f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt ha s th e ca pability of wak ing up th e mi crocontroller whe n it is in sle ep or idl e mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their cont ents should be save d to the me mory at the begi nning of the int errupt servi ce routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.90 ??6 ?e???a?? 18? ?01? rev. 1.90 ?? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom power down mode and wake-up entering the idle or sleep mode there is only one way for the device to enter the sleep or idle mode and that is to execute the "halt" instruction in the application program. when this instruction is executed, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock source and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present condition. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considera tions which must also be taken into account by the circ uit designe r if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator.
rev. 1.90 ?? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pa wu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the re lated in terrupt is fi nally en abled or whe n a sta ck le vel be comes fre e. th e ot her situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.90 ??8 ?e???a?? 18? ?01? rev. 1.90 ?? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low v oltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vl vd0, are used to select one of eight fxed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power , it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low voltage detected 1: low voltage detected bit 4 lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2~vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v
rev. 1.90 ?? 0 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??1 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.4v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.90 ??0 ?e???a?? 18? ?01? rev. 1.90 ?? 1 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the pc0~pc3 or pc0~pc1, pc6~pc7 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by confguring the pc0~pc3 or pc0~pc1, pc6~pc7 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
lcd com bias scomen comnen pin function o/p level 0 x i/o 0 o ? 1 1 0 i/o 0 o ? 1 1 1 scomn v dd / ? output control
rev. 1.90 ??? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. scomc register ? ht66f20 bit 7 6 5 4 3 2 1 0 name d7 isel1 isel0 scomen com ? en com ? en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1, isel0 : select scom typical bias current (v dd =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit 4 scomen : scom module control 0: disable 1: enable bit 3 com3en : pc3 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc2 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pc0 or scom0 selection 0: gpio 1: scom0
rev. 1.90 ??? ?e???a?? 18? ?01? rev. 1.90 ??? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? ht66f30/ht66f40/ht66f50/ht66f60 bit 7 6 5 4 3 2 1 0 name d7 isel1 isel0 scomen com ? en com ? en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1, isel0 : select scom typical bias current (v dd =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit 4 scomen : scom module control 0: disable 1: enable bit 3 com3en : pc7 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc6 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pc0 or scom0 selection 0: gpio 1: scom0
rev. 1.90 ?? 4 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??5 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are select ed they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed s ? stem oscillato ? selection C f h : 1. hxt ? . erc ? . hirc ? low speed s ? stem oscillato ? selection C f l : 1. lxt ? . lirc ? wdt clock selection C f s : 1. f sub ? . f sys /4 4 hirc ?? eq ? enc ? selection: 1. 4mhz ? . 8mhz ? . 1 ? mhz note: the f sub and the f tbc clock so ?? ce a ? e lxt o ? lirc selection ?? the f l confguration option. reset pin options 5 pb0/res pin options: 1. res pin ? . i/o pin watchdog options 6 watchdog time ? ?? nction: 1. ena ? le ? . disa ? le 7 clr wdt inst ?? ctions selection: 1. 1 inst ?? ctions ? . ? inst ?? ctions lvr options 8 lvr ?? nction: 1. ena ? le ? . disa ? le 9 lvr voltage selection: 1. ? .10v ? . ? .55v ? . ? .15v 4. 4. ? 0v sim options 10 sim ?? nction: 1. ena ? le ? . disa ? le 11 spi C wcol ? it: 1. ena ? le ? . disa ? le 1 ? spi C csen ? it: 1. ena ? le ? . disa ? le
rev. 1.90 ??4 ?e???a?? 18? ?01? rev. 1.90 ?? 5 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom no. options 1 ? i ? c de ? o ? nce time selection: 1. no de ? o ? nce ? . 1 s ? stem clock de ? o ? nce ? . ? s ? stem clock de ? o ? nce application circuits

note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant.
rev. 1.90 ?? 6 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??7 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart module serial interface uart module features ? interconnected to holtek mcu via spi interface ? full-duplex, universal asynchronous receiver and transmitter (uar t) communication ? 8 or 9 bit character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect ? address detect interrupt - last character bit=1 ? transmitter and receiver enabled independently ? 4-byte deep fifo receiver data buffer ? transmit and receive multiple interrupt generation sources: C transmitter empty C transmitter idle C receiver full C receiver overrun C address mode detect ? tx pin is high impedance when the uart transmit module is disabled ? rx pin is high impedance when the uart receive module is disabled ? cmos clock input, clki, up to 20mhz at 5v operating voltage uart module overview the device contains a fully embedded full-duplex asynchronous serial communications uart interface that enables data transmission and data reception with external devices. possible applications could include data communication networks between microcontrollers, low-cost data links between pcs and peri pheral devi ces, port able and bat tery ope rated devi ce com munication, factory automation and process control to name but a few. uart module block diagram

rev. 1.90 ??6 ?e???a?? 18? ?01? rev. 1.90 ?? 7 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom pin assignment
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rev. 1.90 ?? 8 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ??9 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom
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rev. 1.90 ??8 ?e???a?? 18? ?01? rev. 1.90 ?? 9 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart module pin description pin name i/o description rx i exte ? nal uart rx se ? ial data inp ? t pin if uarten=1 and rxen=1 ? then rx is the uart se ? ial data inp ? t if uarten=0 o ? rxen=0 ? then rx is high impedance tx o exte ? nal uart tx se ? ial data o ? tp ? t pin if uarten=1 and txen=1 ? then tx is the uart se ? ial data o ? tp ? t if uarten=0 o ? txen=0 ? then tx is high impedance sdi i inte ? nal slave spi se ? ial data in inp ? t signal inte ? nall ? connected to the mcu maste ? spi sdo o ? tp ? t signal sdo o inte ? nal slave spi se ? ial data o ? t o ? tp ? t signal inte ? nall ? connected to the mcu maste ? spi sdi inp ? t signal sck i inte ? nal slave spi se ? ial clock inp ? t signal inte ? nall ? connected to the mcu maste ? spi sck o ? tp ? t signal scs i inte ? nal slave spi device select inp ? t signal inte ? nall ? connected to the mcu maste ? spi scs o ? tp ? t signal -- connected to p ? ll high ? esisto ? clki i inte ? nal clock inp ? t signal inte ? nall ? connected to the mcu maste ? pck o ? tp ? t signal int o inte ? nal uart inte ??? pt o ? tp ? t signal inte ? nall ? connected to the mcu maste ? pint inp ? t signal a uart ? elated inte ??? pt will gene ? ate a low p ? lse signal on this line nc implies that the pin is not connected and can the ? efo ? e not ? e ? sed. notes: the pin description for all pins with the exception of the uart tx and rx pins are described in the preceding mcu section.
rev. 1.90 ? 40 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?41 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart module d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions i dd1 ope ? ating c ??? ent * (spi ena ? led ? uart disa ? led) ? .0v f clki =1 ? mhz ? sck=f clki /4 ? o ? tp ? t no load 1.0 ma 5.0v f clki =16 mhz ? sck=f clki /4 ? o ? tp ? t no load ? .0 ma i dd ? ope ? ating c ??? ent * (spi ena ? led ? uart ena ? led) ? . ? v f clki =6 mhz ? sck=f clki /4 ? o ? tp ? t no load 4. ? ma 5.0v f clki = 1 ? mhz ? sck=f clki /4 ? o ? tp ? t no load 4.8 ma i stb stand ?? c ??? ent * (spi disa ? led ? uart disa ? led) 5.0v f clki =16 mhz ? sck=f clki /4 ? scs=v dd ? uarten=0 ? txen=1 ? rxen=1 ? sdi=h ? rx=h ? o ? tp ? t no load 0.6 a v il inp ? t low voltage fo ? rx po ? ts 0 0. ? v dd v v ih inp ? t high voltage fo ? rx po ? ts 0.7v dd v dd v i ol tx po ? t sink c ??? ent ? .0v v o =0.1v dd ? .5 5.0 ma 5.0v 10.0 ? 5.0 ma i oh rx po ? t so ?? ce c ??? ent ? .0v v o =0.9v dd -1.5 - ? .0 ma 5.0v -5.0 -8.0 ma r ph p ? ll-high resistance fo ? scs onl ? ? .0v ? 0 60 100 k 5.0v 10 ? 0 50 k note: "*" the opera ting curre nt i dd1 listed here is the addi tional curre nt consum ed when the sla ve spi int erface in the uart module is enabled and the uart interface is disabled. similarly, the operating current i dd2 here is the additional current consumed when both the slave spi interface and uart interface are enabled. if the uart module is enabled, either i dd1 or i dd2 should be added to calculate the relevant operating current of the device for different conditions. to calculate the standby current for the whole device, the standby current shown above should be taken into account.
rev. 1.90 ?40 ?e???a?? 18? ?01? rev. 1.90 ? 41 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart module a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions t cp sck pe ? iod (t ch + t cl ) ? .0v 6 ? .5 ns 5.0v 50.0 ns t ch sck high time ? .0 v ? 8 ns 5.0v ?? ns t cl sck low time ? .0v ? 8 ns 5.0v ?? ns t csw scs high p ? lse width ? .0v 500 ns 5.0v 400 ns t css scs to sck set ? p time 100 ns t csh scs to sck hold time 0 ns t sds sdi to sck set ? p time 100 ns t sdh sdi to sck hold time 0 ns t r spi o ? tp ? t rise time 10 ns t ? spi o ? tp ? t ? all time 10 ns t w spi data o ? tp ? t dela ? time 0 ns uart module functional description the embedded uart module is full-duplex asynchronous serial communications uart interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data seriall y by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. interconnection between the mcu and the uart module is implemented by internally connecting the mcu master spi interface to the uart slave spi interface. all data transmissions and receptions between mcu and uart module including uart commands are conduc ted al ong thi s int erconnected spi int erface. the uart funct ion cont rol is executed by the mcu using its spi master serial interface. the uart module contains its own independent interrupt which can be used to indicate when a data reception occurs or when a data transmission has terminated. uart module internal signal in addition to the tx and rx external pins described above there are other mcu to uart module interconnecting lines that are described in the following table. note that these lines are internal to the device and are not bonded to external pins.
rev. 1.90 ? 4 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?4? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mcu to uart internal connection uart module spi interface the mcu communicates with the uart module via an internal spi interface. the spi interface on this device is comprised of four signals: scs (spi chip select), sck (spi clock), sdi (serial data input) and sdo (serial data output). the spi master, which is the mcu, asserts scs by pulling it low to start the data transaction cycle. when the frst 8 bits of data are transmitted, scs should not return to a high level. instead, scs must remain at a low level until the whole 16-bit data transaction is completed. if scs is de-asserted, that is returned to a high level before the 16-bit data transaction is completed, all data bits will be discarded by the uart module spi slave. spi timing both read and write operations are conducted along the spi common interface with the following format: ? write type format: 8-bit command input + 8-bit data input ? read type format: 8-bit command input + 8-bit data output sdo sdi sck scs a7 a6 a5 a4 a? a? a1 a0 d7 d6 d5 d4 d? d? d1 d0 writing type format: 8-bit command input + 8-bit data input sdo sdi sck scs a7 a6 a5 a4 a? a? a1 a0 d7 d6 d5 d4 d? d? d1 d0 t w reading type format: 8-bit command input + 8-bit data output
rev. 1.90 ?4? ?e???a?? 18? ?01? rev. 1.90 ? 4 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom to initiate a da ta tr ansaction, th e mcu ma ster spi ne eds to pu ll scs to a low level frst an d th en also pull sck low. the input data bit on sdi should be stable before the next sck rising edge, as the device will latch the sdi status on the next sck rising edge. regarding the sdo line, the output data bit will be updated on the sck falling edge. the master needs to obtain the line status before the next sck falling edge. there are 16 bits of data transmitted and/or received by the spi interface for each transaction. each transaction co nsists of a co mmand ph ase an d a da ta ph ase. wh en scs is high, the spi int erface is disabled and sdo will be set to a high impedance state. after a complete transaction has been implemented, which requires 16 sck clock cycles, the master needs to set scs to a high level in preparation for the next data transaction. for write operations, the device will begin to execute the command only after it receives a 16-bit serial data sequence and when the scs has been set high again by the master. for read operations, the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. if necessary, the master can de-assert the scs pin to abort the transaction at any time which will cause any data transactions to be abandoned. uart module external pin interfacing to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx pin is the uart transmitter serial data output pin if the corresponding control bits named uarten in ucr1 register and txen in ucr2 register are set to 1. if the control bit uarten or txen is equal to zero, the tx pin is in the state of high impedance. similarly, the rx pin is the uart receiver serial data input pin if the corresponding control bits named uarten and rxen in ucr1 and ucr2 registers are set to 1. if the control bit uarten or rxen is equal to zero, the rx pin is in the state of high impedance. uart data transfer scheme the following block diagram shows the overall data transfer structure arrangement for the uart . the actual dat a to be tra nsmitted from the mcu is first tra nsferred to the txr regi ster by the application program. the data will then be transferred to the transmitter shift register named tsr from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is accessible to the application program, the transmitter shift register is not mapped into the data memory area and is inaccessible to the application program. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb frst, to the receiver shift register named rsr at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is access ible to the application program, the receiver shift register is not mapped into the data memory area and is inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register physically. this shared register known as the txr/rxr register is used for both data transmission and data reception.
rev. 1.90 ? 44 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?45 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart data t?ansfe? scheme msb lsb ?????????? t?ansmitte? shift registe? ( tsr ) msb lsb ?????????? receive? shift registe? ( rsr ) tx pin rx pin ba?d rate gene?ato? tx registe? ( txr ) rx registe? ( rxr ) b?ffe? 1 b?ffe? ? b?ffe? ? data to ?e t?ansmitted data ?eceived uart data transfer scheme uart commands there are both read and write commands for the uart module. for reading and writing to registers both command and address information is contained within a single byte. the format for reading and writing is shown in the following table. command type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read ? i ? o 0 0 0 0 0 read registe ? 0 0 0 1 0 a ? a1 a0 w ? ite ? i ? o 0 0 0 0 1 w ? ite registe ? 0 0 0 1 1 a ? a1 a0 note: "" he ? e stands fo ? don't ca ? e uart status and control registers there are six registers assoc iated wit h the uart functi on. the usr, ucr1, ucr2 and ucr3 registers control the overall function of the uart module, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data register. a[2:0] name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h usr 0000 1011 perr n ? ? err oerr ridle rxi ? tidle txi ? 01h ucr1 0000 000 uarten bno pren prt stops txbrk rx8 tx8 0 ? h ucr ? 0000 0000 txen rxen brgh adden wake rie tiie teie 0 ? h brg brg7 brg6 brg5 brg4 brg ? brg ? brg1 brg0 04h ucr ? 0--- ---- urst 05h~07h un ? sed ---- ---- rese ? ved uart register summary
rev. 1.90 ?44 ?e???a?? 18? ?01? rev. 1.90 ? 45 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom usr register the usr register is the sta tus regi ster for the uart , which can be rea d by the appl ication program to determine the present status of the uart . all fags within the usr register are read only. further explanation on each of the fags is given below: bit 7 6 5 4 3 2 1 0 name perr n ? ? err oerr ridle rxi ? tidle txi ? r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr flag is the parity error flag. when this read only flag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nr flag is th e no ise fl ag. wh en th is re ad on ly fl ag is 0, it in dicates no no ise condition. when the flag is 1, it indicates that the uart has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the nf fag can be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is "0", it indicates that there is no framing error. when the fag is "1" , it indicates that a framing error has been detected for the current character. the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the receiver buffer has overfowed. when this read only fag is 0, it indicates that there is no overrun error. when the fag is 1, it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register. the fag is cleared by a software sequence, which is a read to the status register us r followed by an access to the rxr data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the fag is 1, it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.90 ? 46 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?47 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the rec eive dat a regi ster sta tus fag. whe n thi s rea d only fag is 0, it indicates that the rxr read data register is empty. when the fag is 1, it indicates that the rxr re ad da ta re gister co ntains ne w da ta. wh en th e co ntents of th e shi ft register are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related fags nf, ferr, and/or perr are set within the same clock cycle. the rxif fag is cleared when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : transmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle fag is known as the transmission complete fag. when this read only fag is 0, it indicates that a transmission is in progress. this fag will be set to 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register. the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : transmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicates that the character is not transferred to the transmitter shift register. when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register. the txif fag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif fag bit will also be set since the transmit data register is not yet full.
rev. 1.90 ?46 ?e???a?? 18? ?01? rev. 1.90 ? 47 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uart function such as overall on/off control, parity control, data transfer bit length, etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 name uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 0 ? nknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are in the state of high impedance 1: enable uart. tx and rx pins function as uar t pins the uarten bit is the uart enable bit. when this bit is equal to 0, the uart will be disabled and the rx pin as wel l as the tx pin wil l be in the sta te of high impedance. when the bit is equal to 1, the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uart i s disabl ed, i t wi ll e mpty the buf fer so a ny c haracter re maining i n t he buf fer wi ll be discarded. in addition, the value of the baud rate counter will be reset. if the uart is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and rec eptions wil l b e t erminated and the m odule wi ll b e r eset a s de fned above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is s elected, then bits rx 8 and tx8 w ill be us ed to s tore the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: two stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to 1, two stop bits are used. if this bit is equal to 0, then only one stop bit is used.
rev. 1.90 ? 48 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?49 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 2 txbrk : transmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the tra nsmit bre ak cha racter bit . whe n thi s bit is 0, the re are no break characters and the tx pin operates normally. when the bit is 1, there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : transmit data bit 8 for 9-bit data transfer format (write only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9t h bi t of th e tr ansmitted da ta kn own as tx8 . th e bno bi t is use d to determine whether data transfers are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the uart control registers and serves several purposes. one of its main functions is to control the basic enable/disable operation if the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 name txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 1 0 1 1 bit 7 txen : uart transmitter enable control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txe n is th e tr ansmitter en able bi t. wh en thi s bi t is eq ual to 0, th e transmitter will be disabled with any pending data transmissions being aborted. in addition the buffers will be reset. in this situation the tx pin will be in the state of high impedance. if the txen bit is equal to 1 and the uarten bit is also equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uart . clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. if this situation occurs, the tx pin will be in the state of high impedance. bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to 0, the receiver will be disabled with any pending data receptions being aborted. in addition the receive buffers will be reset. in this situation the rx pin will be in the state of high impedance. if the rxen bit is equal to 1 and the uarten bit is also equal to 1, the receiver will be enabled and the rx pin will be controlled by the uart . clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be in the state of high impedance.
rev. 1.90 ?48 ?e???a?? 18? ?01? rev. 1.90 ? 49 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uart . if this bit is equal to 1, the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bit named adden is th e add ress det ect func tion ena ble con trol bit . whe n th is bit is equal to 1, th e ad dress de tect fu nction is en abled. wh en it oc curs, if th e 8t h bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1, then the received word will be identifed as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on th e va lue of bno. if th e ad dress bi t kno wn as th e 8t h or 9t h bi t of th e received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and the mcu is in idle or sleep mode, a falling edge on the rx input pin will wake-up the device. if this bit is equal to 0 and the mcu is in idle or sleep mode, any edge transitions on the rx pin will not wake-up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the receiver interrupt. if this bit is equal to 1 and when the receiver overrun fag oerr or receive data available fag rxif is set, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : transmitter idle interrupt enable control 0: transmitter idle interrupt is disabled 1: transmitter idle interrupt is enabled this bit enables or disa bles the tra nsmitter idl e int errupt. if thi s bit is equa l to 1 and when the transmitter idl e fag tidl e is set , due to a tra nsmitter idl e condi tion, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : transmitter empty interrupt enable control 0: transmitter empty interrupt is disabled 1: transmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the txif fag.
rev. 1.90 ? 50 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?51 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ucr3 register the ucr3 register is the last of the uart control registers and controls the software reset operation of the uart module. the only one available bit named urst in the uart control register ucr3 is the uart software reset control bit. when this bit is equal to 0, the uart operates normally. if this bit is equal to 1, the whole uart module will be reset. when this situation occurs, the transmitter and receiver will be reset. the uart registers including the status register and control registers will keep the por states shown in the above uart registers table after the reset condition occurs. bit 7 6 5 4 3 2 1 0 name urst r/w r/w por 0 bit 7 urst : uart software reset 0: no action 1: uart reset occurs bit 6~0 unimplemented, read as 0 baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate gene rator. the baud rat e is cont rolled by it s own int ernal free running 8-bit ti mer, the period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value n in the brg register which is used in the following baud rate calculation formula determines the division factor. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 ba ? d rate (br) f clki [64 (n+1)] f clki [16 (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated.
rev. 1.90 ?50 ?e???a?? 18? ?01? rev. 1.90 ? 51 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br= f clki [64 (n+1)] re-arranging this equation gives n= f clki ?1 (br 64) giving a value for n= 4000000 ?1 (4800 64) =12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br= 4000000 [64 (12+1)] =4808 therefore the error is equal to 4808?4800 4800 =0.16% the following tables show the actual values of baud rate and error values for the two value of brgh. 0. ? ? 07 0. ? 00 0.16 185 0. ? 00 0.00 1. ? 51 1. ? 0 ? 0.16 46 1.190 -0.8 ? 9 ? 1. ? 0 ? 0. ?? ? .4 ? 5 ? .404 0.16 ?? ? .4 ?? 1. ?? 46 ? . ? 80 -0.8 ? 4.8 1 ? 4.808 0.16 11 4.661 - ? .90 ?? 4.86 ? 1. ?? 9.6 6 8.9 ? 9 -6.99 5 9. ?? 1 - ? .90 11 9. ??? - ? .90 19. ? ? ? 0.8 ?? 8.51 ? 18.64 ? - ? .90 5 18.64 ? - ? .90 ? 8.4 ? ?? . ? 86 - ? .90 57.6 0 6 ? .500 8.51 0 55.9 ? 0 - ? .90 1 55.9 ? 0 - ? .90 115. ? 0 111.859 - ? .90 ba?d rates and e??o? val?es fo? brgh=0 ba?d rate k/bps ba?d rates fo? brgh=1 f clki =4mhz f clki =?.579545 mhz f clki =7.159mhz brg k?a?d e??o?(%) brg k?a?d e??o?(%) brg k?a?d e??o?(%) 0. ? 1. ? ? 07 1. ? 0 ? 0.16 185 1. ? 0 ? 0. ?? ? .4 10 ? ? .404 0.16 9 ? ? .406 0. ?? 185 ? .406 0. ?? 4.8 51 4.808 0.16 46 4.76 -0.8 ? 9 ? 4.811 0. ?? 9.6 ? 5 9.615 0.16 ?? 9.7 ? 7 1. ?? 46 9.5 ? 0 -0.8 ? 19. ? 1 ? 19. ?? 1 0.16 11 18.64 ? - ? .90 ?? 19.454 1. ?? ? 8.4 6 ? 5.714 -6.99 5 ? 7. ? 86 - ? .90 11 ? 7. ? 86 - ? .90 57.6 ? 6 ? .5 8.51 ? 55.9 ? 0 - ? .90 7 55.9 ? 0 - ? .90 115. ? 1 1 ? 5 8.51 1 111.86 - ? .90 ? 111.86 - ? .90 ? 50 0 ? 50 0 ba?d rates and e??o? val?es fo? brgh=1
rev. 1.90 ? 5 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?5? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom brg register bit 7 6 5 4 3 2 1 0 name brg7 brg6 brg5 brg4 brg ? brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por ? nknown bit 7~0 brg7~brg0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. uart module setup and control for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits and one or two stop bits. parity is supported by the uart hardware and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt , pren and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received lsb frst. although the transmitter and receiver of the uart are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. ? enabling/disabling the uart the basic on/off function of the internal uart function is controlled using the uarten bit in the ucr1 register. if the uarten, txen and rxen bits are set, then these two uart pins will act as normal tx output pin and rx input pin respectively. if no data is being transmitted on the tx pin, then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and these two pins will be in the state of high impedance. when the uart function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset th e en able co ntrol, th e err or an d sta tus fag s wit h bi ts txe n, rxe n, txb rk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration.
rev. 1.90 ?5? ?e???a?? 18? ?01? rev. 1.90 ? 5 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? data, parity and stop bit selection the format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9. the prt bit controls the choice if odd or even parity. the pren bit controls th e pa rity on /off fu nction. th e stops bi t de cides whe ther on e or two sto p bits are to be used. the following table shows various formats for data transmission. the address detect mode control bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.

? uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is obtained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write opera tions. an ac tual tra nsmission of dat a wil l norm ally be ena bled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defned a shift clock source. however, the transmission can also be initiated by frst loading data into the txr register, after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to the high impedance state.
rev. 1.90 ? 54 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?55 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least signifcant bit lsb frst. in the transm it mode , the txr regist er forms a buffer between the in ternal bu s an d th e tr ansmitter shi ft re gister. it sho uld be no ted th at if 9- bit da ta format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the uar t transmitter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register . note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be note d tha t when txif=0, dat a wil l be inhi bited from bei ng writ ten to the txr register. clearing the txif fag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif fag is set by the uart hardware and if set indicates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set, then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immediately set . wh en a fr ame tr ansmission is co mplete, whi ch ha ppens af ter sto p bi ts are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. ? transmitting break if the txbrk bit is set, the n the break chara cters will be sent on the next transm ission. brea k character transmission consists of a start bit, followed by 13n "0" bits, where n=1, 2, etc. if a break character is to be transmitted, then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. transmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continuall y kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized.
rev. 1.90 ?54 ?e???a?? 18? ?01? rev. 1.90 ? 55 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? uart receiver the uart is ca pable of re ceiving wor d le ngths of ei ther 8 or 9 bi ts ca n be sel ected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, will be stored in the rx8 bit in the ucr1 register. at the receiver core lies the receiver shift register more commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the rece ive data regist er, if the regi ster is empt y. the data whic h is received on the ext ernal rx input pin is sam pled thre e ti mes by a ma jority det ect ci rcuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. ? receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin to the shift register, with the least signifcant bit lsb frst. the rxr register is a four byte deep fifo data buffer , where four bytes can be held in the fifo while the 5th byte can continue to be received. note that the applicati on program must ensure that the data is read from rxr before the 5th byte has been completely shifted in, otherwise the 5th byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received, the following sequence of events will occur: ? the rxif bit in the usr register will be set then rxr register has data available, at least three more character can be read. ? when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. a rxr register read execution
rev. 1.90 ? 56 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?57 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? receiving break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as specifed by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specifed by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a val id stop bit before looking for the next start bit . the rec eiver will not ma ke the assumption tha t the brea k condi tion on the li ne is the next start bit . a brea k is rega rded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buffer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. ? idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, wil l hav e a ze ro val ue. in bet ween th e rec eption of a stop bit and th e de tection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. ? receiver interrupt the read onl y rec eive int errupt fag rxif in the usr reg ister is set by an edg e gen erated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1.
rev. 1.90 ?56 ?e???a?? 18? ?01? rev. 1.90 ? 57 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom managing receiver errors several types of reception errors can occur w ithin the u art module, the follow ing s ection des cribes the various types and how they are managed by the uart. ? overrun error C oerr fag the rxr register is composed of a four byte deep fifo data buffer, where four bytes can be held in the fifo register, while a 5th byte can continue to be received. before the 5th byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the oerr fag can be cleared by an access to the usr register followed by a read to the rxr register. ? noise error C nf fag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame, the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf fag is reset by a usr register read operation followed by an rxr register read operation. ? framing error C ferr fag the read only framing error fag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high. otherwise the ferr fag will be set. the ferr fag is buf fered along with the received data and is cleared in any reset. ? parity error C perr fag the read only parity error fag, perr, in the usr register, is set if the parity of the received word is incorrect. this error fag is only applicable if the parity function is enabled, pren=1, and if the parity type, odd or even, is selected. the read only perr fag is buffered along with the received data bytes. it is cleared on any reset, it should be noted that the ferr and perr fags are buffered along with the corresponding word and should be read before reading the data word.
rev. 1.90 ? 58 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?59 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom uart module interrupt structure several individual uart con ditions ca n gen erate a uart int errupt. whe n th ese con ditions exi st, a low pulse wil l be genera ted on the int line to get the at tention of the mi crocontroller. the se conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. four of these conditions have the corresponding usr register fags which will generate a uart interrupt if its associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart int errupt source, does not have an associate d flag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by set ting the adden bit in the ucr2 regi ster. an rx pin wake -up, whic h is al so a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a falling edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay, commonly known as the system start-up time, for the oscillator to restart and stabilize before the system resumes normal operation. note that the usr re gister fl ags ar e re ad on ly an d ca nnot be cl eared or set by th e ap plication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when ce rtain ac tions are ta ken by the uart , the det ails of whic h are giv en in the uart register sect ion. the overall uart int errupt can be disable d or enabl ed by the relat ed interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed.
? ? ?? ? ? ? ?? ? ? ? ? ? - ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? - ? ? uart module interrupt structure
rev. 1.90 ?58 ?e???a?? 18? ?01? rev. 1.90 ? 59 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? address detect mode setting the address detect function enable control bit, adden, in the ucr2 register, enables this special function. if this bit is set to 1, then an additional qualifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif fag. if the adden bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit of the microcontroller must also be enabled for correct interrupt generation. the highest address bit is the 9th bit if the bit bno=1 or the 8th bit if the bit bno=0. if the highest bit is high, then the rec eived word wil l be defi ned as an ad dress rat her tha n dat a. a dat a ava ilable interrupt will be generated every time the last bit of the received word is set. if the adden bit is equal to 0, then a receive data a vailable interrupt will be generated each time the rxif fag is set, irrespective of the data last but status. the address detect and parity functions are mutually exclusive functions. therefore if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit pren to zero. adden bit 9 (bno=1) bit 8 (bno=0) uart interrupt generated 0 0 1 1 0 1 adden bit function uart module power-down and wake-up the mcu an d uart mod ule ar e po wered do wn in dependently of ea ch ot her. th e me thod of powering down the mcu is covered in the previous mcu section of the datasheet. the uart module must be po wered do wn be fore th e mcu is po wered do wn. th is is im plemented by fi rst clearing the uarten bit in the ucr1 register to disable the uart module circuitry after which the scs internal line can be set high to disable the sp i interface circuits. when the ua rt and spi interfaces are powered down, the sck and clki clock sources to the uart module will be disabled. the uart module can be powered up by the mcu by frst clearing the scs line to zero and then setting the uarten bit. if the uart circuits is powered down while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the uart circuits is powered down while receiving data, then the reception of data will likewise be terminated. when the uart circuits is powered down, note that the usr, ucr1, ucr2, ucr3, transmit and receive registers, as well as the brg register will not be affected. the uart module contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register . if this bit, along with the uart enable bit named uarten, the receiver ena ble bit nam ed rxen and the rec eiver int errupt ena ble bit nam ed rie, are al l set before the mcu and uart module are is powered down, then a falling edge on the rx pin will wake up the mcu from its power down condition. note that as it takes a certain period of time known as the system start-up time for oscillator to restart and stabilize after a wake-up, any data received during this time on the rx pin will be ignored. for a uart wake -up int errupt to occ ur, in add ition to the bit s for the wake -up ena ble con trol and receive interrupt enable control being set, the global interrupt enable control and the related interrupt enable control bits must also be set. if these two bits are not set, then only a wake-up event will occur and no interrupt will be serviced. note also that as it takes a period of delay after a wake- up before normal microcontroller resumes, the relevant uart interrupt will not be serviced until this period of delay time has elapsed.
rev. 1.90 ? 60 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?61 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom using the uart function to use the uart function, several important steps must be implemented to ensure that the uart module operates normally: ? the spi pin-remapping function must be properly confgured when the spi functional pins of the microcontroller are used to control the uart module and for data transmission and data reception. to correctly connect the mcu master spi to the uart module slave spi, the sim pin-remapping settings for pck and pint in the mcu prm0 register should be the same as the values listed in the following table. ? ht66fu30 C prm0 register C pck and pint pin-remap setup bit 1 0 name simps0 pckps setting val ? e 1 1 ? ht66fu40/ht66fu50 C prm0 register C pck and pint pin-remap setup bit 2 1 0 name simps1 simps0 pckps setting val ? e 0 1 1 ? HT66FU60 C prm0 register C pck and pint pin-remap setup bit 2 1 0 name simps1 simps0 pckps setting val ? e 1 1 1 ? the sim operating mode control bits sim2~sim0, in the simc0 register have to be confgured to enable the sim to operate in the spi master mode with a different spi clock frequency. ? sim operating mode control bits sim2~sim0 in the simc0 register bit 2 1 0 name sim ? sim1 sim0 val ? e 100 ? 011 ? 010 ? 001 ? 000 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101~111: must not be used
rev. 1.90 ?60 ?e???a?? 18? ?01? rev. 1.90 ? 61 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ? the pck control bit is set to 1 to enable the pck output as the clock source for the uart baud rate generator with various pck output frequencies determined by the pckp1 and pckp0 bits in the simc0 register. ? pck output frequency selection bits pckp1~pckp0 in the simc0 register bit 3 2 name pckp1 pckp0 val ? e 11 ? 10 ? 01 ? 00 00: pck output frequency is f sys 01: pck output frequency is f sys /4 10: pck output frequency is f sys /8 11: pck output frequency is tm0 ccrp match frequency/2 ? pck output enable control bit pcken in the simc0 register bit 4 name pcken val ? e 1 0: disable pck output 1: enable pck output after the above setup conditions have been implemented, the mcu can enable the sim interface by setting the simen bit high. the mcu can then begin communication with external uart connected devices using its spi interface. the detailed mcu master spi functional description is provided within the serial interface module section of the mcu datasheet. application circuit with uart module
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? note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant.
rev. 1.90 ? 6 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?6? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented wit hin 0.5s and branc h or ca ll inst ructions would be im plemented wit hin 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to tha t new addre ss, one more cyc le wil l be requi red. exa mples of such inst ructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of dat a wit hin the mi crocontroller program is one of the most freque ntly used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most im portant dat a tra nsfer appl ications is to rec eive dat a from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller appl ications. wi thin the holt ek mi crocontroller inst ruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.90 ?6? ?e???a?? 18? ?01? rev. 1.90 ? 6 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holt ek mi crocontroller inst ruction set. as wit h the ca se of most inst ructions invol ving data manipulation, da ta mu st pa ss th rough th e acc umulator whi ch ma y in volve ad ditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming app lications where dat a ca n be rota ted from an int ernal regi ster int o the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call inst ruction. the y dif fer in the sense tha t in the ca se of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. thi s is done by pla cing a ret urn inst ruction re t in the subrouti ne which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a ce rtain dat a me mory or indi vidual bit s. depe nding upon the condi tions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to dec ision ma king and branc hing wit hin the program perha ps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is norma lly im plemented by using regi sters. however, when working wit h la rge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.90 ? 64 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?65 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memo ?? to acc 1 z ? c ? ac ? ov addm a ? [m] add acc to data memo ?? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data memo ?? to acc with ca ??? 1 z ? c ? ac ? ov adcm a ? [m] add acc to data memo ?? with ca ??? 1 note z ? c ? ac ? ov sub a ? x s ?? t ? act immediate data f ? om the acc 1 z ? c ? ac ? ov sub a ? [m] s ?? t ? act data memo ?? f ? om acc 1 z ? c ? ac ? ov subm a ? [m] s ?? t ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov sbc a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ??? 1 z ? c ? ac ? ov sbcm a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov daa [m] decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 1 note c logic operation and a ? [m] logical and data memo ?? to acc 1 z or a ? [m] logical or data memo ?? to acc 1 z xor a ? [m] logical xor data memo ?? to acc 1 z andm a ? [m] logical and acc to data memo ?? 1 note z orm a ? [m] logical or acc to data memo ?? 1 note z xorm a ? [m] logical xor acc to data memo ?? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data memo ?? 1 note z cpla [m] complement data memo ?? with ? es ? lt in acc 1 z increment & decrement inca [m] inc ? ement data memo ?? with ? es ? lt in acc 1 z inc [m] inc ? ement data memo ?? 1 note z deca [m] dec ? ement data memo ?? with ? es ? lt in acc 1 z dec [m] dec ? ement data memo ?? 1 note z rotate rra [m] rotate data memo ?? ? ight with ? es ? lt in acc 1 none rr [m] rotate data memo ?? ? ight 1 note none rrca [m] rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc 1 c rrc [m] rotate data memo ?? ? ight th ? o ? gh ca ??? 1 note c rla [m] rotate data memo ?? left with ? es ? lt in acc 1 none rl [m] rotate data memo ?? left 1 note none rlca [m] rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc 1 c rlc [m] rotate data memo ?? left th ? o ? gh ca ??? 1 note c
rev. 1.90 ?64 ?e???a?? 18? ?01? rev. 1.90 ? 65 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mnemonic description cycles flag affected data move mov a ? [m] move data memo ?? to acc 1 none mov [m] ? a move acc to data memo ?? 1 note none mov a ? x move immediate data to acc 1 none bit operation clr [m].i clea ? ? it of data memo ?? 1 note none set [m].i set ? it of data memo ?? 1 note none branch jmp add ? j ? mp ? nconditionall ? ? none sz [m] skip if data memo ?? is ze ? o 1 note none sza [m] skip if data memo ?? is ze ? o with data movement to acc 1 note none sz [m].i skip if ? it i of data memo ?? is ze ? o 1 note none snz [m].i skip if ? it i of data memo ?? is not ze ? o 1 note none siz [m] skip if inc ? ement data memo ?? is ze ? o 1 note none sdz [m] skip if dec ? ement data memo ?? is ze ? o 1 note none siza [m] skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none sdza [m] skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none call add ? s ??? o ? tine call ? none ret ret ?? n f ? om s ??? o ? tine ? none ret a ? x ret ?? n f ? om s ??? o ? tine and load immediate data to acc ? none reti ret ?? n f ? om inte ??? pt ? none table read tabrd [m] read ta ? le to tblh and data memo ?? ? note none tabrdl [m] read ta ? le (last page) to tblh and data memo ?? ? note none miscellaneous nop no ope ? ation 1 none clr [m] clea ? data memo ?? 1 note none set [m] set data memo ?? 1 note none clr wdt clea ? watchdog time ? 1 to ? pd ? clr wdt1 p ? e-clea ? watchdog time ? 1 to ? pd ? clr wdt ? p ? e-clea ? watchdog time ? 1 to ? pd ? swap [m] swap ni ?? les of data memo ?? 1 note none swapa [m] swap ni ?? les of data memo ?? with ? es ? lt in acc 1 none halt ente ? powe ? down mode 1 to ? pd ? note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution sta tus. the to and pdf fla gs are cl eared aft er both c lr wdt 1 and c lr wdt 2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.90 ? 66 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?67 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom instruction defnition adc a,[m] add da ta me mory to ac c wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] + c affected fag(s) ov, z, ac , c adcm a,[m] add ac c to da ta me mory wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] + c affected fag(s) ov, z, ac , c add a,[m] add da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] affected fag(s) ov, z, ac , c add a,x add immediate d ata to ac c description the co ntents of th e ac cumulator an d th e sp ecifed imm ediate da ta ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + x affected fag(s) ov, z, ac , c addm a,[m] add ac c to da ta me mory description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] affected fag(s) ov, z, ac , c and a,[m] logical an d da ta memor y to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d [m ] affected fag(s) z and a,x logical and imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wi se lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d x affected fag(s) z andm a,[m] logical an d ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c a nd [m] affected fag(s) z
rev. 1.90 ?66 ?e???a?? 18? ?01? rev. 1.90 ? 67 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom call addr subroutine ca ll description unconditionally cal ls a su broutine at th e sp ecifed ad dress. the pr ogram cou nter th en increments by 1 to ob tain th e ad dress of th e ne xt in struction wh ich is th en pu shed on to th e stack. th e spe cifed add ress i s th en l oaded an d th e pro gram co ntinues ex ecution fro m th is new add ress. as th is in struction req uires an add itional ope ration, i t i s a tw o cy cle in struction. operation stack pr ogram c ounter + 1 program cou nter ad dr affected fag(s) none clr [m] clear da ta memor y description each bi t of th e sp ecifed da ta me mory is clea red to 0. operation [m] 0 0h affected fag(s) none clr [m].i clear bit of da ta me mory description bit i of th e sp ecifed da ta me mory is clea red to 0. operation [m].i 0 affected fag(s) none clr wdt clear wa tchdog ti mer description the to , pd f fag s an d th e wd t ar e all cl eared. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt1 pre-clear wa tchdog ti mer description the to , pd f fa gs an d th e wd t are al l cl eared. no te th at th is in struction wo rks in conjunction wit h cl r wd t2 an d mu st be ex ecuted alt ernately wit h cl r wd t2 to ha ve effect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t2 wi ll have no ef fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt2 pre-clear wa tchdog ti mer description the to , pd f fa gs a nd th e wd t a re al l c leared. no te th at thi s in struction wo rks in c onjunction with cl r wd t1 an d mu st be ex ecuted alt ernately wit h cl r wd t1 to ha ve ef fect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t1 wi ll ha ve no e f fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f cpl [m] complement da ta memor y description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. operation [m] [m] affected fag(s) z
rev. 1.90 ? 68 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?69 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom cpla [m] complement da ta me mory wit h re sult in ac c description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. the co mplemented re sult is sto red in the ac cumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc [m] affected fag(s) z daa [m] decimal-adjust ac c fo r ad dition wit h re sult in da ta me mory description convert th e co ntents of th e ac cumulator val ue to a bc d (b inary co ded de cimal) val ue resulting fro m th e pre vious add ition of tw o bc d va riables. if th e l ow ni bble i s g reater th an 9 or if ac fag is se t, th en a val ue of 6 wi ll be ad ded to th e lo w ni bble. ot herwise th e lo w ni bble remains un changed. if th e hi gh ni bble is gr eater th an 9 or if th e c fag is se t, th en a val ue of 6 will be ad ded to th e hi gh ni bble. es sentially, th e de cimal co nversion is pe rformed by ad ding 00h, 06 h, 60 h or 66 h de pending on th e ac cumulator an d fag co nditions. on ly th e c fag may be af fected by th is in struction wh ich in dicates th at i f th e or iginal bc d su m i s g reater th an 100, it all ows mul tiple pr ecision de cimal ad dition. operation [m] ac c + 0 0h o r [m] ac c + 06h or [m] ac c + 6 0h or [m] ac c + 6 6h affected fag(s) c dec [m] decrement da ta memor y description data in th e sp ecifed da ta me mory is dec remented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement da ta memor y wit h re sult in ac c description data in th e spe cifed da ta me mory i s de cremented by 1. th e res ult i s st ored in th e accumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] ? 1 affected fag(s) z halt enter po wer d own mo de description this in struction sto ps th e pr ogram ex ecution an d tu rns of f th e sy stem cl ock. the co ntents of the da ta me mory an d re gisters ar e re tained. the wd t an d pr escaler ar e cl eared. the po wer down fag pd f is se t an d th e wd t tim e-out fag to is cl eared. operation to 0 pdf 1 affected fag(s) to, pd f inc [m] increment da ta memor y description data in th e spe cifed da ta me mory i s in cremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memor y wit h re sult in ac c description data in th e spe cifed da ta me mory is in cremented by 1. the res ult is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] + 1 affected fag(s) z
rev. 1.90 ?68 ?e???a?? 18? ?01? rev. 1.90 ? 69 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom jmp addr jump unconditionally description the co ntents of th e pro gram co unter are rep laced wi th th e spe cifed add ress. pro gram execution th en co ntinues fro m th is ne w add ress. as th is req uires th e in sertion of a du mmy instruction wh ile th e ne w add ress i s l oaded, i t i s a tw o cy cle in struction. operation program c ounter ad dr affected fag(s) none mov a,[m] move da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. operation acc [m ] affected fag(s) none mov a,x move immediate d ata to ac c description the imm ediate da ta sp ecifed is lo aded in to th e ac cumulator. operation acc x affected fag(s) none mov [m],a move ac c to da ta me mory description the co ntents of th e ac cumulator ar e co pied to th e sp ecifed da ta me mory. operation [m] ac c affected fag(s) none nop no op eration description no op eration is pe rformed. ex ecution con tinues wi th th e ne xt in struction. operation no o peration affected fag(s) none or a,[m] logical or da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise logical or ope ration. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r [m ] affected fag(s) z or a,x logical o r imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r x affected fag(s) z orm a,[m] logical o r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c o r [m] affected fag(s) z ret return f rom su broutine description the pro gram co unter i s res tored fro m th e st ack. pro gram ex ecution co ntinues at th e res tored a dd ress. operation program c ounter st ack affected fag(s) none
rev. 1.90 ? 70 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?71 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ret a,x return fr om sub routine a nd lo ad imm ediate d ata to ac c description the pr ogram cou nter is re stored fr om th e sta ck an d th e ac cumulator lo aded wit h th e sp ecifed immediate da ta. pr ogram ex ecution co ntinues at th e re stored ad dress. operation program c ounter st ack acc x affected fag(s) none reti return f rom in terrupt description the pro gram co unter i s res tored fro m th e st ack an d th e in terrupts are re- enabled by se tting th e emi bit . em i is th e ma ster in terrupt gl obal en able bit . if an in terrupt wa s pe nding wh en th e reti in struction i s ex ecuted, th e pe nding int errupt rou tine wi ll be pro cessed be fore ret urning to th e ma in pro gram. operation program c ounter st ack emi 1 affected fag(s) none rl [m] rotate da ta memor y le ft description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i=0~6) [m].0 [m] .7 affected fag(s) none rla [m] rotate data me mory l eft wi th res ult in ac c description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e da ta me mory re main u ncha nged. operation acc.(i+1) [m ].i; ( i=0~6) acc.0 [m ].7 affected fag(s) none rlc [m] rotate data me mory le ft th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated le ft by 1 bit . bit 7 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i=0~6) [m].0 c c [m] .7 affected fag(s) c rlca [m] rotate da ta me mory l eft th rough ca rry wi th res ult in ac c description data in th e sp ecifed da ta me mory a nd th e c arry fa g a re ro tated le ft by 1 bit . bit 7 re places th e carry bit an d th e or iginal ca rry fag is ro tated in to th e bit 0. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.(i+1) [m ].i; ( i=0~6) acc.0 c c [m] .7 affected fag(s) c rr [m] rotate data memor y ri ght description the c ontents o f th e sp ecifed da ta me mory a re ro tated ri ght by 1 bit wit h bit 0 ro tated in to bit 7. operation [m].i [m ].(i+1); ( i=0~6) [m].7 [m] .0 affected fag(s) none
rev. 1.90 ?70 ?e???a?? 18? ?01? rev. 1.90 ? 71 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom rra [m] rotate data me mory r ight w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit wit h bit 0 rotated in to bit 7. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e data memor y rema in uncha nged. operation acc.i [m ].(i+1); ( i=0~6) acc.7 [m ].0 affected fag(s) none rrc [m] rotate data me mory ri ght th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. operation [m].i [m ].(i+1); ( i=0~6) [m].7 c c [m] .0 affected fag(s) c rrca [m] rotate da ta me mory r ight thr ough ca rry w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 re places the ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.i [m ].(i+1); ( i=0~6) acc.7 c c [m] .0 affected fag(s) c sbc a,[m] subtract da ta memor y f rom ac c wit h ca rry description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e ac cumulator. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] ? c affected fag(s) ov, z, ac , c sbcm a,[m] subtract da ta memor y f rom ac c wit h ca rry and re sult in da ta memor y description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e da ta me mory. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] ? c affected fag(s) ov, z, ac , c sdz [m] skip if de crement da ta me mory is 0 description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0 th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] ? 1 skip if [m ]=0 affected fag(s) none
rev. 1.90 ? 7 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?7? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom sdza [m] skip if de crement da ta me mory is zer o wit h re sult in ac c description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e re sult i s no t 0, the pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] ? 1 skip if ac c=0 affected fag(s) none set [m] set da ta memor y description each bi t of th e sp ecifed da ta memor y is set to 1. operation [m] ff h affected fag(s) none set [m].i set bit of data memor y description bit i of th e sp ecifed da ta memor y is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment da ta memor y is 0 description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] + 1 skip if [m ]=0 affected fag(s) none siza [m] skip i f in crement da ta me mory i s ze ro wi th res ult in ac c description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] + 1 skip if ac c=0 affected fag(s) none snz [m].i skip if bit i o f da ta me mory is no t 0 description if bi t i of th e spe cifed da ta me mory i s no t 0, th e fo llowing in struction i s sk ipped. as th is requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i 0 affected fag(s) none sub a,[m] subtract da ta memor y f rom ac c description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] affected fag(s) ov, z, ac , c
rev. 1.90 ?7? ?e???a?? 18? ?01? rev. 1.90 ? 7 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom subm a,[m] subtract da ta memor y f rom ac c wit h re sult in da ta memor y description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e da ta me mory. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] affected fag(s) ov, z, ac , c sub a,x subtract immediate d ata fr om ac c description the imm ediate da ta sp ecifed by th e co de is su btracted fr om th e co ntents of th e ac cumulator. the res ult i s st ored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fag wi ll be cl eared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? x affected fag(s) ov, z, ac , c swap [m] swap nibbles o f da ta me mory description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. operation [m].3~[m].0 ? [m] .7~[m].4 affected fag(s) none swapa [m] swap nib bles o f da ta me mory wit h re sult in ac c description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. the result is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc.3~acc.0 [m ].7~[m].4 acc.7~acc.4 [m ].3~[m].0 affected fag(s) none sz [m] skip if data me mory is 0 description if th e c ontents o f th e sp ecifed da ta me mory is 0 , th e f ollowing in struction is sk ipped. as thi s requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ]=0 affected fag(s) none sza [m] skip if data me mory is 0 wit h d ata mo vement to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. if th e val ue is ze ro, the fo llowing in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction while th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e program pro ceeds wi th th e fo llowing in struction. operation acc [m ] skip if [m ]=0 affected fag(s) none sz [m].i skip if bit i o f da ta me mory is 0 description if bi t i of th e spe cifed da ta me mory i s 0, th e fo llowing in struction i s sk ipped. as th is req uires the in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle instruction. if th e res ult i s no t 0, th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i=0 affected fag(s) none
rev. 1.90 ? 74 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?75 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom tabrd [m] read tab le (cu rrent pag e) to tb lh an d da ta me mory description the low by te of th e pro gram co de (c urrent pa ge) add ressed by th e ta ble po inter (t blp) i s moved to th e sp ecifed da ta memor y an d th e hi gh byt e mov ed to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none tabrdl [m] read table ( last pa ge) to tb lh and da ta memor y description the low byt e of th e pro gram co de ( last pa ge) ad dressed by th e ta ble po inter ( tblp) is mov ed to th e sp ecifed da ta me mory an d th e hi gh by te mo ved to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none xor a,[m] logical xo r da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r [m ] affected fag(s) z xorm a,[m] logical xo r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c x or [m] affected fag(s) z xor a,x logical xor imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r x affected fag(s) z
rev. 1.90 ?74 ?e???a?? 18? ?01? rev. 1.90 ? 75 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supp lementary i nformation wi th r egard t o pac kaging i s l isted be low. cl ick o n t he r elevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.90 ? 76 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?77 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 16-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? ? 0.045 0.070 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a 19.81 ?? . ? 5 b 6.10 7.11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 ? 1.14 1.78 g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ?76 ?e???a?? 18? ?01? rev. 1.90 ? 77 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 0.7 ? 5 0.775 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? ? 0.045 0.070 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a 18.67 19.69 b 6.10 7.11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 ? 1.14 1.78 g ? .54 h 7.6 ? 8. ? 6 i 10.9 ? mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.745 0.785 b 0. ? 75 0. ? 95 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? ? 0.045 0.060 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a 18.9 ? 19.94 b 6.99 7.49 c ? .05 ? .81 d ? .79 ? .81 e 0. ? 6 0.56 ? 1.14 1.5 ? g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ? 78 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?79 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.01 ? 0.0 ? 0 c 0. ? 86 0.40 ? d 0.069 e 0.050 ? 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0.51 c 9.80 10. ? 1 d 1.75 e 1. ? 7 ? 0.10 0. ? 5 g 0.41 1. ? 7 h 0.18 0. ? 5 0 8
rev. 1.90 ?78 ?e???a?? 18? ?01? rev. 1.90 ? 79 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0.189 0.197 d 0.054 0.060 e 0.0 ? 5 ? 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 4.80 5.00 d 1. ? 7 1.5 ? e 0.64 ? 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8
rev. 1.90 ? 80 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?81 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 20-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? ? 0.045 0.070 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 4.89 ? 6.9 ? b 6.10 7.11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 ? 1.14 1.78 g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ?80 ?e???a?? 18? ?01? rev. 1.90 ? 81 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.945 0.985 b 0. ? 75 0. ? 95 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? ? 0.045 0.060 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 4.00 ? 5.0 ? b 6.99 7.49 c ? .05 ? .81 d ? .79 ? .81 e 0. ? 6 0.56 ? 1.14 1.5 ? g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ? 8 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?8? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.496 0.51 ? d 0.104 e 0.050 ? 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 1 ? .60 1 ? .00 d ? .64 e 1. ? 7 ? 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8
rev. 1.90 ?8? ?e???a?? 18? ?01? rev. 1.90 ? 8 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.01 ? c 0. ?? 5 0. ? 47 d 0.049 0.065 e 0.0 ? 5 ? 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c 8.51 8.81 d 1. ? 4 1.65 e 0.64 ? 0.10 0. ? 5 g 0. ? 8 1. ? 7 h 0.18 0. ? 5 0 8
rev. 1.90 ? 84 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?85 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 24-pin skdip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 1. ?? 0 1. ? 80 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? ? 0.045 0.070 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 1. ? 4 ?? .51 b 6.10 7.11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 ? 1.14 1.78 g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ?84 ?e???a?? 18? ?01? rev. 1.90 ? 85 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? ? 0.045 0.070 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 9.46 ? 0. ? 5 b 6.10 7.11 c ? .9 ? 4.95 d ? .9 ? ? .81 e 0. ? 6 0.56 ? 1.14 1.78 g ? .54 h 7.6 ? 8. ? 6 i 10.9 ? mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0. ? 75 0. ? 95 c 0.1 ? 0 0.150 d 0.110 0.150 e 0.014 0.0 ?? ? 0.045 0.060 g 0.100 h 0. ? 00 0. ?? 5 i 0.4 ? 0 symbol dimensions in mm min. nom. max. a ? 9.08 ? 0.10 b 6.99 7.49 c ? .05 ? .81 d ? .79 ? .81 e 0. ? 6 0.56 ? 1.14 1.5 ? g ? .54 h 7.6 ? 8. ? 6 i 10.9 ?
rev. 1.90 ? 86 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?87 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.598 0.61 ? d 0.104 e 0.050 ? 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 15.19 15.57 d ? .64 e 1. ? 7 ? 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8
rev. 1.90 ?86 ?e???a?? 18? ?01? rev. 1.90 ? 87 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0. ?? 5 0. ? 46 d 0.054 0.060 e 0.0 ? 5 ? 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 8.51 8.79 d 1. ? 7 1.5 ? e 0.64 ? 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8
rev. 1.90 ? 88 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?89 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1. ? 75 1. ? 95 b 0. ? 78 0. ? 98 c 0.1 ? 5 0.1 ? 5 d 0.1 ? 5 0.145 e 0.016 0.0 ? 0 ? 0.050 0.070 g 0.100 h 0. ? 95 0. ? 15 i 0. ? 75 symbol dimensions in mm min. nom. max. a ? 4.9 ? ? 5.4 ? b 7.06 7.57 c ? .18 ? .4 ? d ? .18 ? .68 e 0.41 0.51 ? 1. ? 7 1.78 g ? .54 h 7.49 8.00 i 9.5 ?
rev. 1.90 ?88 ?e???a?? 18? ?01? rev. 1.90 ? 89 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ? 56 0. ? 00 c 0.01 ? 0.0 ? 0 c 0.697 0.71 ? d 0.104 e 0.050 ? 0.004 0.01 ? g 0.016 0.050 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6 ? c 0. ? 0 0.51 c 17.70 18.11 d ? .64 e 1. ? 7 ? 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8
rev. 1.90 ? 90 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?91 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c 0. ? 86 0. ? 94 d 0.054 0.060 e 0.0 ? 5 ? 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c 9.80 10.01 d 1. ? 7 1.5 ? e 0.64 ? 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0 8
rev. 1.90 ?90 ?e???a?? 18? ?01? rev. 1.90 ? 91 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom saw type 32-pin (5mm5mm) qfn outline dimensions asecl symbol dimensions in inch min. nom. max. a 0.0 ? 8 0.0 ? 1 a1 0.000 0.001 0.00 ? a ? 0.008 ? 0.007 0.010 0.01 ? d 0.197 e 0.197 e 0.0 ? 0 d ? 0.1 ?? 0.1 ? 0 e ? 0.1 ?? 0.1 ? 0 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.70 0.80 a1 0.00 0.0 ? 0.05 a ? 0. ? 0 ? 0.18 0. ? 5 0. ? 0 d 5.00 e 5.00 e 0.50 d ? ? .10 ? . ? 0 e ? ? .10 ? . ? 0 l 0. ? 5 0.40 0.45 k 0. ? 0
rev. 1.90 ? 9 ? ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?9? ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom saw type 40-pin (6mm6mm) qfn outline dimensions gtk symbol dimensions in inch min. nom. max. a 0.0 ? 8 0.0 ? 0 0.0 ? 1 a1 0.000 0.001 0.00 ? a ? 0.008 ? 0.007 0.010 0.01 ? d 0. ?? 6 e 0. ?? 6 e 0.0 ? 0 d ? 0.17 ? 0.177 0.179 e ? 0.17 ? 0.177 0.179 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.7 0.75 0.8 a1 0.00 0.0 ? 0.05 a ? 0. ? 0 ? 0.18 0. ? 5 0. ? 0 d 6.00 e 6.00 e 0.50 d ? 4.40 4.50 4.55 e ? 4.40 4.50 4.55 l 0. ? 5 0.40 0.45 k 0. ? 0
rev. 1.90 ?9? ?e???a?? 18? ?01? rev. 1.90 ? 9 ? ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 44-pin lqfp (10mm10mm) (fp 2.0mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 0.476 b 0. ? 90 0. ? 98 c 0.469 0.476 d 0. ? 90 0. ? 98 e 0.0 ? 1 ? 0.01 ? g 0.05 ? 0.057 h 0.06 ? i 0.004 j 0.018 0.0 ? 0 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 11.90 1 ? .10 b 9.90 10.10 c 11.90 1 ? .10 d 9.90 10.10 e 0.80 ? 0. ? 0 g 1. ? 5 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0. ? 0 0 7
rev. 1.90 ? 94 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?95 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 48-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 95 0.4 ? 0 b 0. ? 91 0. ? 99 c 0.008 0.01 ? c 0.61 ? 0.6 ? 7 d 0.085 0.099 e 0.0 ? 5 ? 0.004 0.010 g 0.0 ? 5 0.0 ? 5 h 0.004 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 10.0 ? 10.67 b 7. ? 9 7.59 c 0. ? 0 0. ? 0 c 15.57 16.18 d ? .16 ? .51 e 0.64 ? 0.10 0. ? 5 g 0.64 0.89 h 0.10 0. ? 0 0 8
rev. 1.90 ?94 ?e???a?? 18? ?01? rev. 1.90 ? 95 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom saw type 48-pin (7mm7mm) qfn outline dimensions asecl symbol dimensions in inch min. nom. max. a 0.0 ? 1 0.0 ?? 0.0 ? 5 a1 0.000 0.001 0.00 ? a ? 0.008 ? 0.007 0.010 0.01 ? d 0. ? 76 e 0. ? 76 e 0.0 ? 0 d ? 0. ? 19 0. ??? 0. ?? 6 e ? 0. ? 19 0. ??? 0. ?? 6 l 0.014 0.016 0.018 symbol dimensions in mm min. nom. max. a 0.800 0.850 0.900 a1 0.000 0.0 ? 5 0.050 a ? 0. ? 0 ? ? 0.180 0. ? 50 0. ? 00 d 7.000 e 7.000 e 0.500 d ? 5.550 5.650 5.750 e ? 5.550 5.650 5.750 l 0. ? 50 0.400 0.450
rev. 1.90 ? 96 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 ?97 ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 50 0. ? 58 b 0. ? 7 ? 0. ? 80 c 0. ? 50 0. ? 58 d 0. ? 7 ? 0. ? 80 e 0.0 ? 0 ? 0.008 g 0.05 ? 0.057 h 0.06 ? i 0.004 j 0.018 0.0 ? 0 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 8.9 9.1 b 6.9 7.1 c 8.9 9.1 d 6.9 7.1 e 0.5 ? 0. ? g 1. ? 5 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0. ? 0 0 7
rev. 1.90 ?96 ?e???a?? 18? ?01? rev. 1.90 ? 97 ? e ??? a ?? 18 ? ? 01 ? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom 52-pin qfp (14mm14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.681 0.689 b 0.547 0.555 c 0.681 0.689 d 0.547 0.555 e 0.0 ? 9 ? 0.016 g 0.098 0.1 ?? h 0.1 ? 4 i 0.004 j 0.0 ? 9 0.041 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 17. ? 0 17.50 b 1 ? .90 14.10 c 17. ? 0 17.50 d 1 ? .90 14.10 e 1.00 ? 0.40 g ? .50 ? .10 h ? .40 i 0.10 j 0.7 ? 1.0 ? k 0.10 0. ? 0 0 7
rev. 1.90 ? 98 ? e ??? a ?? 18 ? ? 01 ? rev. 1.90 pb ?e???a?? 18? ?01? ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom ht66f20/ht66f30/ht66f40/ht66f50/ht66f60 ht66fu30/ht66fu40/ht66fu50/HT66FU60 enhanced a/d flash type 8-bit mcu with eeprom holtek semiconductor inc. (headquarters) no. ?? c ? eation rd. ii ? science pa ? k ? hsinch ?? taiwan tel: 886- ? -56 ? -1999 ? ax: 886- ? -56 ? -1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4 ? - ?? no. ? - ?? y ? anq ? st. ? nankang softwa ? e pa ? k ? taipei 115 ? taiwan tel: 886- ? - ? 655-7070 ? ax: 886- ? - ? 655-7 ? 7 ? ? ax: 886- ? - ? 655-7 ? 8 ? (inte ? national sales hotline) holtek semiconductor (china) inc. (dongguan sales offce) b ? ilding no.10 ? xinzh ? co ?? t ? (no.1 headq ? a ? te ? s) ? 4 c ? izh ? road ? songshan lake ? dongg ? an ? china 5 ?? 808 tel: 86-769- ? 6 ? 6-1 ? 00 ? ax: 86-769- ? 6 ? 6-1 ? 11 ? 86-769- ? 6 ? 6-1 ??? holtek semiconductor (usa), inc. (north america sales offce) 467 ? 9 ?? emont blvd. ? ?? emont ? ca 945 ? 8 ? usa tel: 1-510- ? 5 ? -9880 ? ax: 1-510- ? 5 ? -9885 http://www.holtek.com cop ?? ight ? ? 01 ? ?? holtek semiconductor inc. the info ? mation appea ? ing in this data sheet is ? elieved to ? e acc ?? ate at the time of p ?? lication. howeve ?? holtek ass ? mes no ? esponsi ? ilit ? a ? ising f ? om the ? se of the specifications desc ? i ? ed. the applications mentioned he ? ein a ? e ? sed solel ? fo ? the p ?? pose of ill ? st ? at ion and holtek makes no wa ?? ant ? o ? ? ep ? esentation that s ? ch applications will ? e s ? ita ? le witho ? t f ?? the ? modification ? no ? ? ecommends the ? se o f its p ? o d ? cts fo ? a pplication that ma ? p ? esen t a ? i sk to h ? man life d ? e to malf ? nc tion o ? ot he ? wise. holtek's p ? od ? c ts a ? e not a ? t ho ? ized f o ? ? se as c ? itic al components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most ? p-to-date info ? mation ? please visit o ?? we ? site at http://www.holtek.com .

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